参数资料
型号: ADM1067ACPZ
厂商: Analog Devices Inc
文件页数: 22/32页
文件大小: 0K
描述: IC SEQUENCER/SUPERVISOR 40-LFCSP
标准包装: 1
系列: Super Sequencer®
类型: 序列发生器
监视电压数目: 10
输出: 可编程
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP-VQ(6x6)
包装: 托盘
配用: EVAL-ADM1067TQEBZ-ND - BOARD EVALUATION FOR ADM1067TQ
ADM1067
The output voltage is given by the following equation:
DAC Output = ( DACx ? 0x7F)/255 × 0.6015 + V OFF
where V OFF is one of the four offset voltages.
There are 256 DAC settings available. The midcode value is
located at DAC Code 0x7F, as close as possible to the middle
of the 256 code range. The full output swing of the DACs is
+302 mV (+128 codes) and ?300 mV (?127 codes) around the
selected midcode voltage. The voltage range for each midcode
voltage is shown in Table 9.
This equation demonstrates that if the user wants the output
voltage to change by ±300 mV, R1 = R3. If the user wants the
output voltage to change by ±600 mV, R1 = 2 × R3, and so on.
It is best to use the full DAC output range to margin a supply.
Choosing the attenuation resistor in this way provides the most
resolution from the DAC, meaning that with one DAC code
change, the smallest effect on the dc-to-dc converter output
voltage is induced. If the resistor is sized up to use a code such as
27 decimal to 227 decimal to move the dc-to-dc converter output
by ±5%, it takes 100 codes to move 5% (each code moves the
Table 9. Ranges for Midcode Voltages
Midcode Minimum Voltage
Voltage (V) Output (V)
Maximum Voltage
Output (V)
output by 0.05%). This is beyond the readback accuracy of the
ADC, but it should not prevent the user from building a circuit
to use the most resolution.
0.6
0.8
1.0
1.25
0.300
0.500
0.700
0.950
0.902
1.102
1.302
1.552
DAC LIMITING AND OTHER SAFETY FEATURES
Limit registers (called DPLIMx and DNLIMx) on the device offer
the user some protection from firmware bugs that can cause
catastrophic board problems by forcing supplies beyond their
CHOOSING THE SIZE OF THE ATTENUATION
RESISTOR
The size of the attenuation resistor, R3, determines how much
the DAC voltage swing affects the output voltage of the dc-to-dc
converter that is being margined.
Because the voltage at the feedback pin remains constant, the
current flowing from the feedback node to GND through R2 is
a constant. In addition, the feedback node itself is high impedance.
This means that the current flowing through R1 is the same as
the current flowing through R3. Therefore, a direct relationship
exists between the extra voltage drop across R1 during margining
and the voltage drop across R3.
This relationship is given by the following equation:
allowable output ranges. Essentially, the DAC code written into
the DACx register is clipped such that the code used to set the
DAC voltage is actually given by
DAC Code
= DACx, DACx ≥ DNLIMx and DACx ≤ DPLIMx
= DNLIMx, DACx < DNLIMx
= DPLIMx, DACx > DPLIMx
In addition, the DAC output buffer is three-stated, if DNLIMx >
DPLIMx. By programming the limit registers this way, the user
can make it very difficult for the DAC output buffers to be turned
on during normal system operation. The limit registers are among
the registers downloaded from the EEPROM at startup.
Δ V OUT =
R1
R3
( V FB ? V DACOUT )
where:
Δ V OUT is the change in V OUT .
V FB is the voltage at the feedback node of the dc-to-dc converter.
V DACOUT is the voltage output of the margining DAC.
Rev. D | Page 22 of 32
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