参数资料
型号: ADM1067ACPZ
厂商: Analog Devices Inc
文件页数: 28/32页
文件大小: 0K
描述: IC SEQUENCER/SUPERVISOR 40-LFCSP
标准包装: 1
系列: Super Sequencer®
类型: 序列发生器
监视电压数目: 10
输出: 可编程
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP-VQ(6x6)
包装: 托盘
配用: EVAL-ADM1067TQEBZ-ND - BOARD EVALUATION FOR ADM1067TQ
ADM1067
SMBus PROTOCOLS FOR RAM AND EEPROM
The ADM1067 contains volatile registers (RAM) and nonvolatile
registers (EEPROM). User RAM occupies Address 0x00
to Address 0xDF; the EEPROM occupies Address 0xF800 to
Address 0xFBFF.
Data can be written to and read from both the RAM and the
EEPROM as single data bytes. Data can be written only to
unprogrammed EEPROM locations. To write new data to a
programmed location, the location contents must first be erased.
EEPROM erasure cannot be done at the byte level. The
EEPROM is arranged as 32 pages of 32 bytes each, and an entire
page must be erased.
?
To erase a page of EEPROM memory. EEPROM memory
can be written to only if it is unprogrammed. Before writing
to one or more EEPROM memory locations that are already
programmed, the page(s) containing those locations must
first be erased. EEPROM memory is erased by writing a
command byte.
The master sends a command code telling the slave device
to erase the page. The ADM1067 command code for a page
erasure is 0xFE (1111 1110). Note that for a page erasure to
take place, the page address must be given in the previous
write word transaction (see the Write Byte/Word section).
In addition, Bit 2 in the UPDCFG register (Address 0x90)
must be set to 1.
Page erasure is enabled by setting Bit 2 in the UPDCFG register
1
2
3
4
5
6
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
S
SLAVE
ADDRESS
W
A
COMMAND
BYTE
(0xFE)
A
P
the SMBus.
WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in Figure 33 to Figure 41:
Figure 34. EEPROM Page Erasure
As soon as the ADM1067 receives the command byte, page
erasure begins. The master device can send a stop command
as soon as it sends the command byte. Page erasure takes ap-
proximately 20 ms. If the ADM1067 is accessed before erasure
?
?
?
?
?
?
S = Start
P = Stop
R = Read
W = Write
A = Acknowledge
A = No acknowledge
is complete, it responds with a no acknowledge (NACK).
Write Byte/Word
In a write byte/word operation, the master device sends a
command byte and one or two data bytes to the slave device,
as follows:
1. The master device asserts a start condition on SDA.
The ADM1067 uses the following SMBus write protocols.
Send Byte
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
2.
3.
4.
5.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an ACK on SDA.
The master sends a command code.
The slave asserts an ACK on SDA.
1.
2.
3.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an acknowledge (ACK)
6.
7.
8.
9.
The master sends a data byte.
The slave asserts an ACK on SDA.
The master sends a data byte or asserts a stop condition.
The slave asserts an ACK on SDA.
on SDA.
10. The master asserts a stop condition on SDA to end the
4.
The master sends a command code.
transaction.
5. The slave asserts an ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
In the ADM1067, the send byte protocol is used for two purposes
? To write a register address to the RAM for a subsequent
single byte read from the same address, or for a block read
In the ADM1067, the write byte/word protocol is used for three
purposes:
? To write a single byte of data to the RAM. In this case, the
command byte is RAM Address 0x00 to RAM Address 0xDF,
and the only data byte is the actual data, as shown in Figure 35.
or block write starting at that address, as shown in Figure 33.
1
2
3
4
5
6
7 8
SLAVE
S ADDRESS W A
1
S
2
SLAVE
ADDRESS
W
3
A
4
RAM
ADDRESS
(0x00 TO 0xDF)
5
A
6
P
RAM
ADDRESS A DATA A P
(0x00 TO 0xDF)
Figure 35. Single Byte Write to the RAM
Figure 33. Setting a RAM Address for Subsequent Read
Rev. D | Page 28 of 32
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