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| 型号： | ADP1850DP-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/32页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ADP1850DP |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.09V |
| 电流 - 输出： | 50A |
| 输入电压： | 10 ~ 15 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP1850DP |
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Data Sheet
MODES OF OPERATION
The SYNC pin is a multifunctional pin. PWM mode is enabled
ADP1850
when SYNC is connected to VCCO or a high logic. With SYNC
connected to ground or left floating, the pulse skip mode is
enabled. Switching SYNC from low to high or high to low on
the fly causes the controller to transition from forced PWM
to pulse skip mode or pulse skip mode to forced PWM, respec-
tively, in two clock cycles.
Table 5. Mode of Operation Truth Table
SYNC Pin Mode of Operation
Low
Pulse skip mode
1
2
3
4
DH1
DL1
OUTPUT
RIPPLE
INDUCTOR CURRENT
High
No Connect
Clock Signal
Forced PWM or two-phase operation
Pulse skip mode
Forced PWM or two-phase operation
CH1 10V CH2 5V M1μs A CH1 13.4V
CH3 20mV CH4 2A ?
Figure 25. Example of Discontinuous Conduction Mode (DCM) Waveform
In forced PWM, the ADP1850 always operates in CCM at any
The ADP1850 has a pulse skip sensing circuitry that allows the
controller to skip PWM pulses, thus, reducing the switching
frequency at light loads and, therefore, maintaining high
efficiency during a light load operation. The switching
frequency is a fraction of the natural oscillator frequency and
is automatically adjusted to regulate the output voltage. The
resulting output ripple is larger than that of the fixed frequency
forced PWM. Figure 24 shows that the ADP1850 operates in
PSM under a very light load. Pulse skip frequency under light
load is dependent on the inductor, output capacitance, output
load, and input and output voltages.
SW1
1
COMP1 (CH2)
load. The inductor current is always continuous, thus, efficiency
is poor at light loads.
SYNCHRONIZATION
The switching frequency of the ADP1850 can be synchronized
to an external clock by connecting SYNC to a clock signal. The
external clock should be between 1× and 2.3× of the internal
oscillator frequency, f SW . The resulting switching frequency is ?
of the external SYNC frequency because the SYNC input is
divided by 2, and the resulting phases are used to clock the two
channels alternately. In synchronization, the ADP1850 operates
in PWM.
When an external clock is detected at the first SYNC edge, the
internal oscillator is reset, and the clock control shifts to SYNC.
The SYNC edges then trigger subsequent clocking of the PWM
outputs. The DH1/DH2 rising edges appear approximately 100 ns
after the corresponding SYNC edge, and the frequency is locked
3
4
2
VOUT RIPPLE
INDUCTOR
CURRENT
to the external signal. Depending on the start-up conditions of
Channel 1 and Channel 2, either Channel 1 or Channel 2 can be
the first channel synchronized to the rising edge of the SYNC
clock. If the external SYNC signal disappears during operation,
the ADP1850 reverts to its internal oscillator. When the SYNC
function is used, it is recommended to connect a pull-up resistor
CH1 10V
CH2 200mV
M200μs
A CH1
7.8V
from SYNC to VCCO so that when the SYNC signal is lost, the
CH3 20mV
CH4 2A ?
ADP1850 continues to operate in PWM.
Figure 24. Example of Pulse Skip Mode Under Light Load
When the output load is greater than the pulse skip threshold
current, that is, V COMP reaches the threshold of 0.9 V, the
ADP1850 exits the pulse skip mode of operation and enters
the fixed frequency discontinuous conduction mode (DCM),
as shown in Figure 25. When the load increases further, the
ADP1850 enters CCM.
Rev. A | Page 13 of 32
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