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| 型号： | ADP1850DP-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/32页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ADP1850DP |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.09V |
| 电流 - 输出： | 50A |
| 输入电压： | 10 ~ 15 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP1850DP |
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= R BOT ? ? OUT
? V ? V FB ?
?
R TOP ?
ADP1850
APPLICATIONS INFORMATION
SETTING THE OUTPUT VOLTAGE
The output voltage is set using a resistive voltage divider from
the output to FB. The voltage divider divides down the output
voltage to the 0.6 V FB regulation voltage to set the regulation
output voltage. The output voltage can be set to as low as 0.6 V
and as high as 90% of the power input voltage.
The maximum input bias current into FB is 100 nA. For a 0.15%
degradation in regulation voltage and with 100 nA bias current,
the low-side resistor, R BOT , must be less than 9 kΩ, which results
in 67 μA of divider current. For R BOT , use a 1 kΩ to 20 kΩ resistor.
A larger value resistor can be used but results in a reduction in
output voltage accuracy due to the input bias current at the FBx
pin, while lower values cause increased quiescent current
consumption. Choose R TOP to set the output voltage by using
the following equation:
? V FB ?
where:
R TOP is the high-side voltage divider resistance.
R BOT is the low-side voltage divider resistance.
V OUT is the regulated output voltage.
V FB is the feedback regulation threshold, 0.6 V.
The minimum output voltage is dependent on f SW and minimum
DH on time. The maximum output voltage is dependent on f SW ,
the minimum DH off time, and the IR drop across the high-side
NMOSFET and the DCR of the inductor. For example, with f SW of
600 kHz (or 1.67 μs) and a minimum on time of 130 ns, the
minimum duty cycle is approximately 7.8% (130 ns/1.67 μs). If
V IN is 12 V and the duty cycle is 7.8%, then the lowest output is
0.94 V. As an example for the maximum output voltage, if V IN is
5 V, f SW is 600 kHz, and the minimum DH off time is 395 ns
Data Sheet
The SSx pin reaches a final voltage equal to VCCO. If the output
voltage is precharged prior to turn-on, the ADP1850 prevents
reverse inductor current, which discharges the output capacitor.
Once the voltage at SSx exceeds the regulation voltage (typically
0.6 V), the reverse current is reenabled to allow the output
voltage regulation to be independent of load current.
Furthermore, in dual-phase operation, where SS1 is shorted to
SS2, the current source is doubled to 13 μA during the soft start
sequence.
When a controller is disabled, for instance, EN1/EN2 is pulled
low or experiences an overcurrent limit condition, the soft start
capacitor is discharged through an internal 3 kΩ pull-down
resistor.
SETTING THE CURRENT LIMIT
The current limit comparator measures the voltage across the
low-side MOSFET to determine the load current.
The current limit is set by an external current limit resistor,
R ILIM , between ILIMx and SWx. The current sense pin, ILIMx,
sources nominally 50 μA to this external resistor. This creates an
offset voltage of R ILIM multiplied by 50 μA. When the drop
across the low-side MOSFET, R DSON , is equal to or greater than
this offset voltage, the ADP1850 flags a current limit event.
Because the ILIMx current and the MOSFET, R DSON , vary over
process and temperature, the minimum current limit should be
set to ensure that the system can handle the maximum desired
load current. To do this, use the peak current in the inductor,
which is the desired output current limit level plus ? of the
ripple current, the maximum R DSON of the MOSFET at its
highest expected temperature, and the minimum ILIM current.
Keep in mind that the temperature coefficient of the MOSFET,
R DSON , is typically 0.4%/ o C.
(335 ns DH off time plus approximately 60 ns total dead time),
then the maximum duty cycle is 76%. Therefore, the maximum
output is approximately 3.8 V. If the IR drop across the high-
R ILIM =
I LPK × R DSON _ MAX
47 μ A
side NMOSFET and the DCR of the inductor is 0.5 V, then the
absolute maximum output is 4.5 V (5 V ? 0.5 V), independent of
f SW and duty cycle.
SOFT START
The soft start period is set by an external capacitor between
SS1/SS2 and AGND. The soft start function limits the input
inrush current and prevents output overshoot.
When EN1/EN2 is enabled, a current source of 6.5 μA starts
charging the capacitor, and the regulation voltage is reached
when the voltage at SS1/SS2 reaches 0.6 V.
The soft start period is approximated by
where:
I LPK is the peak inductor current.
t SS =
0.6 V
6 . 5 μA
C SS
Rev. A | Page 16 of 32
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