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参数资料
| 型号： | ADP1850DP-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/32页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ADP1850DP |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.09V |
| 电流 - 输出： | 50A |
| 输入电压： | 10 ~ 15 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP1850DP |
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Data Sheet
ADP1850
SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). V IN = 12 V. The
specifications are valid for T J = ?40°C to +125°C, unless otherwise specified. Typical values are at T A = 25°C.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
Input Voltage
V IN
2.75
20
V
Undervoltage Lockout Threshold
IN UVLO
V IN rising
2.45
2.6
2.75
V
Undervoltage Lockout Hysteresis
V IN falling
2.4
2.5
0.1
2.6
V
Quiescent Current
I IN
EN1 = EN2 = V IN = 12 V, V FB = V CCO in PWM mode
4.5
5.8
mA
(no switching)
EN1 = EN2 = V IN = 12 V, V FB = V CCO in PSM mode
2.8
mA
Shutdown Current
I IN_SD
EN1 = EN2 = GND, V IN = 5.5 V or 20 V
100
200
μ A
ERROR AMPLIFIER
FBx Input Bias Current
I FB
?100
+1
+100
nA
Transconductance
TRK1, TRK2 Input Bias Current
CURRENT SENSE AMPLIFIER GAIN
G m
I TRK
A CS
Sink or source 1 μA
0 V ≤ V TRK1 /V TRK2 ≤ 5 V
Gain resistor connected to DLx,
385
?100
2.4
550
+1
3
715
+100
3.6
μS
nA
V/V
R CSG = 47 kΩ ± 5%
Gain resistor connected to DLx,
5.2
6
6.9
V/V
R CSG = 22 kΩ ± 5%
Default setting, R CSG = open
Gain resistor connected to DLx,
10.5
20.5
12
24
13.5
26.5
V/V
V/V
R CSG = 100 kΩ ± 5%
OUTPUT CHARACTERICTISTICS
Feedback Accuracy Voltage
V FB
T J = ?40 ° C to +85 ° C, V FB = 0.6 V
T J = ?40 ° C to +125 ° C, V FB = 0.6 V
?0.85%
?1.5%
+0.6
+0.6
+0.85%
+1.5%
V
V
Line Regulation of PWM
ΔV FB /ΔV IN
±0.015
%/V
Load Regulation of PWM
ΔV FB /ΔV COMP
V COMP range = 0.9 V to 2.2 V
±0.3
%
OSCILLATOR
Frequency
SYNC Input Frequency Range
f SW
f SYNC
R FREQ = 340 kΩ to AGND
R FREQ = 78.7 kΩ to AGND
R FREQ = 39.2 kΩ to AGND
FREQ to AGND
FREQ to VCCO
f SYNC = 2 × f SW
170
720
1275
235
475
400
200
800
1500
300
600
235
880
1725
345
690
3000
kHz
kHz
kHz
kHz
kHz
kHz
SYNC Input Pulse Width
SYNC Pin Capacitance to GND
t SYNCMIN
C SYNC
100
5
ns
pF
LINEAR REGULATOR
VCCO Output Voltage
VCCO Load Regulation
VCCO Line Regulation
VCCO Current Limit 1
VCCO Short-Circuit Current 1
VIN to VCCO Dropout Voltage 2
V DROPOUT
I VCCO = 100 mA
I VCCO = 0 mA to 100 mA,
V IN = 5.5 V to 20 V, I VCCO = 20 mA
VCCO drops to 4 V from 5 V
VCCO < 0.5 V
I VCCO = 100 mA, V IN ≤ 5 V
4.7
5.0
35
10
350
370
0.33
5.3
400
V
mV
mV
mA
mA
V
LOGIC INPUTS
EN1, EN2
EN1/EN2 rising
0.57
0.63
0.68
V
EN1, EN2 Hysteresis
0.03
V
EN1, EN2 Input Leakage Current
I EN
V IN = 2.75 V to 20 V
1
200
nA
SYNC Logic Input Low
SYNC Logic Input High
1.9
1.3
V
V
SYNC Input Pull-Down Resistance
R SYNC
1
MΩ
Rev. A | Page 3 of 32
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