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| 型号： | ADP1850DP-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/32页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ADP1850DP |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.09V |
| 电流 - 输出： | 50A |
| 输入电压： | 10 ~ 15 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP1850DP |
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ADP1850
CONFIGURATION AND LOOP COMPENSATION
(DUAL-PHASE OPERATION)
In dual-phase operation, the two outputs of the switching
regulators are shorted together and can source more than
50 A of output current depending on the selection of the
power components. Internal parameters in the ADP1850
are optimized and trimmed in the factory to minimize the
mismatch in output currents between the two channels. See
phase application circuit. Note that FB1 shorts to FB2, SS1 to
SS2, and COMP1 to COMP2, where the outputs of the two
error amplifiers are shared. Furthermore, the controller needs
to be placed in forced PW M operation by connecting SYNC
to VCCO or logic high.
The equations for calculating the loop compensation com po-
nents are identical to the single-phase operation, but the
combined value of G m of the error amplifiers, t he modulator
Data Sheet
SWITCHING NOISE AND OVERSHOOT REDUCTION
In any high speed step-down regulator, high frequency noise
(generally in the range of 50 MHz to 100 MHz) and voltage
overshoot are always present at the gate, the switch node (SW),
and the drains of the external MOSFETs. The high frequency
noise and overshoot are caused by the parasitic capacitance,
C GD , of the external MOSFET and the parasitic inductance of
the gate trace and the packages of the MOSFETs. When the high
current is switched, electromagnetic interference (EMI) is
generated, which can affect the operation of the surrounding
circuits. To reduce voltage ringing and noise, it is recommended
to add an RC snubber between SWx and PGNDx for high current
In most applications, R SNUB is typically 2 Ω to 4 Ω, and C SNUB
typically 1.2 nF to 3 nF.
R SNUB can be estimated by
gain and the effective f SW are all doubled.
V IN
R RAMP1
R SNUB ? 2
L MOSFET
C OSS
And C SNUB can be estimated by
DH1
BST1
VCCO
PGND1
HI
LO
RAMP1 VIN
ADP1850
EN1
EN2
VDL
SW1
ILIM1
FB1
TRK1
TRK2
PGOOD1 DL1
PGOOD2
SYNC
FREQ
RAMP2
COMP1
DH2
COMP2
BST2
R CSG1
R RAMP2
M1
M2
M3
L1
V IN
L2
V OUTx
C SNUB ? C OSS
where :
L MOSFET is the total parasitic inductance of the high-side and
low-side MOSFETs, typically 3 nH, and is package dependent.
C OSS is the total output capacitance of the high-side and low-
side MOSFETs given in the MOSFET data sheet.
The size of the RC snubber components needs to be chosen
correctly to handle the power dissipation. The power dissipated
in R SNUB is
P SNUB = V IN 2 × C SNUB × f SW
SW2
ILIM2
FB2
R1
In most applications, a component size 0805 for R SNUB is sufficient.
However, the use of an RC snubber reduces the overall efficiency,
SS1
SS2
DL2
R CSG2
M4
R2
generally by an amount in the range of 0.1% to 0.5%. The RC
snubber does not reduce the voltage overshoot. A resistor,
AGND
PGND2
Figure 34. Dual-Phase Circuit
shown as R RISE in Figure 35, at the BSTx pin helps to reduce
overshoot and is generally between 2 Ω and 4 Ω. Adding a
resistor in series, typically between 2 Ω and 4 Ω, with the gate
driver also helps to reduce overshoot. If a gate resistor is added,
then R RISE is not needed.
VDL
ADP1850
(CHANNEL 1)
BST1
R RISE
V IN
DH1
SW1
M1
L
V OUTx
ILIM1
DL1
R ILIM1
M2
R SNUB
C SNUB
C OUT
PGND1
Figure 35. Application Circuit with a Snubber
Rev. A | Page 22 of 32
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