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参数资料
| 型号： | ADP1850DP-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/32页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ADP1850DP |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.09V |
| 电流 - 输出： | 50A |
| 输入电压： | 10 ~ 15 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP1850DP |
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Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP1850
EN1
SYNC
1
2
24
23
SW1
DH1
VIN
VCCO
VDL
AGND
FREQ
EN2
3
4
5
6
7
8
ADP1850
TOP VIEW
(Not to Scale)
22
21
20
19
18
17
PGND1
DL1
DL2
PGND2
DH2
SW2
NOTES
1. CONNECT THE BOTTOM EXPOSED PAD OF THE
LFCSP PACKAGE TO SYSTEM AGND PLANE.
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
EN1
SYNC
VIN
VCCO
VDL
AGND
FREQ
EN2
TRK2
FB2
COMP2
RAMP2
SS2
PGOOD2
Description
Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive EN1 low to turn off the
Channel 1 controller. Tie EN1 to VIN for automatic startup. For a precision UVLO, put an appropriately sized
resistor divider from VIN to AGND and tie the midpoint to this pin.
Frequency Synchronization Input. Accepts an external signal between 1× and 2.3× of the internal oscillator
frequency, f SW , set by the FREQ pin. The controller operates in forced PWM when a signal is detected at SYNC or
when SYNC is high. The resulting switching frequency is ? of the SYNC frequency. When SYNC is low or left
floating, the controller operates in pulse skip mode. For dual-phase operation, connect SYNC to a logic high or an
external clock.
Connect to Main Power Supply. Bypass with a 1 μF or larger ceramic capacitor connected as close to this pin as
possible and PGNDx.
Output of the Internal Low Dropout Regulator (LDO). Bypass VCCO to AGND with a 1 μF or larger ceramic
capacitor. The VCCO output remains active even when EN1 and EN2 are low. For operation with VIN below 5 V,
VIN may be shorted to VCCO. Do not use the LDO to power other auxiliary system loads.
Power Supply for the Low-Side Driver. Bypass VDL to PGNDx with a 1 μF or greater ceramic capacitor. Connect
VCCO to VDL.
Analog Ground.
Sets the desired operating frequency between 200 kHz and 1.5 MHz with one resistor between FREQ and AGND.
Connect FREQ to AGND for a preprogrammed 300 kHz or FREQ to VCCO for 600 kHz operating frequency.
Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive EN2 low to turn off the
Channel 2 controller. Tie EN2 to VIN for automatic startup. For a precision UVLO, put an appropriately sized
resistor divider from VIN to AGND, and tie the midpoint to this pin.
Tracking Input for Channel 2. Connect TRK2 to VCCO if tracking is not used.
Output Voltage Feedback for Channel 2. Connect to Output 2 via a resistor divider.
Compensation Node for Channel 2. Output of Channel 2 error amplifier. Connect a series resistor-capacitor
network from COMP2 to AGND to compensate the regulation control loop.
Connect a resistor from RAMP2 to VIN to set up a ramp current for slope compensation in Channel 2. The voltage
at RAMP2 is 0.2 V. This pin is high impedance when the channel is disabled.
Soft Start Input for Channel 2. Connect a capacitor from SS2 to AGND to set the soft start period. The node is
internally pulled up to 5 V with a 6.5 μA current source.
Power Good. Open-drain power-good indicator logic output with an internal 12 kΩ resistor connected between
PGOOD2 and VCCO. PGOOD2 is pulled to ground when the Channel 2 output is outside the regulation window.
An external pull-up resistor is not required.
Rev. A | Page 7 of 32
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