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参数资料
| 型号： | ADP5020CP-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL PMU IMAGING ADP5020 |
| 设计资源： | Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135) |
| 标准包装： | 1 |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 3，非隔离 |
| 输出电压： | 3.3V，1.2V，1.8V |
| 电流 - 输出： | 600mA，250mA，150mA |
| 输入电压： | 2.4 ~ 5.5 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 3MHz |
| 板类型： | 完全填充 |
| 已供物品： | 2 板，CD |
| 已用 IC / 零件： | ADP5020 |
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ADP5020
Table 15. REG_CONTROL_STATUS Register, Address 0x03
Bit
7
6
5
4
Bit Name
BK1_EN
BK2_EN
LDO_EN
EN_ALL
Access
R/W
R/W
R/W
R/W
Default
0
0
0
0
Description
1 = turns on the Buck 1 regulator. If the EN pin is high, the sequencer is ignored.
1 = turns on the Buck 2 regulator. If the EN pin is high, the sequencer is ignored.
1 = turns on the LDO regulator. If the EN pin is high, the sequencer is ignored.
1 = turns on all regulators, following sequencer programming. BK1_EN, BK2_EN, and
LDO_EN must all be set to 0 for this bit to function.
3
BK1_PGOOD
R
0
Power good status for Buck 1.
1 = power good (POK).
0 = fail.
2
BK2_PGOOD
R
0
Power good status for Buck 2.
1 = power good (POK).
0 = fail.
1
LDO_PGOOD
R
0
Power good status for LDO.
1 = power good (POK).
0 = fail.
0
FORCE_XS
R/W
0
1 = the XSHTDN pin is controlled by the power good signals.
0 = the XSHTDN pin is held low unless the EN pin is high, regardless of regulator status.
If EN is high, this bit is ignored in controlling the XSHTDN pin (acts as if FORCE_XS = 1).
Table 16. OPERATIONAL_CONTROL Register, Address 0x04
Bit
7
6
Bit Name
Reserved
SYNC_9P6 1
Access
N/A
R/W
Default
N/A
0
Description
Reserved.
1 = a 9.6 MHz clock is on the SYNC pin. The SYNC frequency is divided by 3 and used as
clock frequency for switching regulators.
5
SYNC_19P2 1
R/W
0
1 = a 19.2 MHz clock is on the SYNC pin. The SYNC frequency is divided by 6 and used as
clock frequency for switching regulators.
1 for both SYNC_9P6 and SYNC_19P2 = invalid setting.
0 for both SYNC_9P6 and SYNC_19P2 = clock synchronization is disabled, and the device
operates with the 3 MHz internal clock.
4
SYNC_AC 1
R/W
0
1 = the ac path is used for the SYNC input.
0 = the dc path is used (default).
3
BK1_XSHTDN
R/W
Fuse
0 = power good for Buck 1 must be high for XSHTDN to go high (default).
1 = Buck 1 power good is ignored.
2
BK2_XSHTDN
R/W
Fuse
0 = power good for Buck 2 must be high for XSHTDN to go high (default).
1 = Buck 2 power good is ignored.
1
LDO_XSHTDN
R/W
Fuse
0 = LDO power good must be high for XSHTDN to go high (default).
1 = LDO power good is ignored.
0
TSD
R/W
0
Shows a latched status of a thermal shutdown (TSD) event.
1 = TSD is active.
Must be cleared to 0 by user program to enable the regulators. If this bit remains set to 1,
regulator activation is inhibited, as in a thermal shutdown event.
1
The SYNC selection bits (SYNC_AC, SYNC_9P6, and SYNC_19P2) cannot be changed while a switching regulator is running.
Table 17. EN_CONTROL Register, Address 0x05
Bit
[7:2]
1
Bit Name
Reserved
ENO_HIZ_BAR
Access
N/A
R/W
Default
N/A
0
Description
Reserved.
0 = the EN/GPIO pin is in high impedance, and the EN function is selected.
1 = GPIO output is selected, and the EN function is ignored.
0
ENO_DRV
R/W
0
Active only when ENO_HIZ_BAR = 1 (GPIO).
0 = GPIO output is set to low.
1 = GPIO output is set to high.
Rev. 0 | Page 16 of 28
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相关代理商/技术参数 |
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|---|---|
| ADP5022 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 3 MHz, 600 mA Buck Regulator with 150 mA LDO |
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