参数资料
型号: ADP5020CP-EVALZ
厂商: Analog Devices Inc
文件页数: 9/28页
文件大小: 0K
描述: BOARD EVAL PMU IMAGING ADP5020
设计资源: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
标准包装: 1
主要目的: DC/DC,LDO 步降
输出及类型: 3,非隔离
输出电压: 3.3V,1.2V,1.8V
电流 - 输出: 600mA,250mA,150mA
输入电压: 2.4 ~ 5.5 V
稳压器拓扑结构: 降压
频率 - 开关: 3MHz
板类型: 完全填充
已供物品: 2 板,CD
已用 IC / 零件: ADP5020

ADP5020
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VOUT1 15
VOUT1 14
VDD3 13
VOUT3 12
EN/GPIO 11
ADP5020
BOTTOM VIEW
(Not to Scale)
EXPOSED PAD
1 PGND2
2 VOUT2
3 VDDA
4 AGND
5 SYNC
PGND2 1
VOUT2 2
VDDA 3
AGND 4
PIN 1
INDICATOR
ADP5020
TOP VIEW
(Not to Scale)
15 VOUT1
14 VOUT1
13 VDD3
12 VOUT3
NOTES
1. EXPOSED PAD SHOULD BE CONNECTED
TO PGND1 AND PGND2.
SYNC 5
11 EN/GPIO
Figure 4. Pin Configuration (Bottom View)
Table 9. Pin Function Descriptions
Figure 5. Pin Configuration (Top View)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14, 15
16
17
18
19
20
EPAD
Mnemonic
PGND2
VOUT2
VDDA
AGND
SYNC
DGND
SDA
SCL
VDD_IO
XSHTDN
EN/GPIO
VOUT3
VDD3
VOUT1
PGND1
SW1
VDD1
VDD2
SW2
Exposed paddle
Description
Power Ground Buck 2.
Feedback Buck 2.
Supply Voltage Internal Analog Circuit.
Analog Ground.
Frequency Synchronization. Connect to an external 19.2 MHz or 9.6 MHz clock signal to synchronize the
internal oscillator.
Digital Ground.
I 2 C Data.
I 2 C Clock.
Supply Voltage for Internal Logic Inputs/Outputs.
Shutdown Output, Active Low.
After power-on reset, this pin is defined as enable (EN). To enable active high, the I 2 C command can program
this pin to be an output (GPIO). A weak pull-down resistor is enabled when the pin operates as EN.
Regulated Output Voltage from LDO.
Supply Voltage LDO.
Feedback/Driver Buck 1 Output.
Power Ground Buck 1.
Switch Pin Buck 1.
Supply Voltage Buck 1.
Supply Voltage Buck 2.
Switch Pin Buck 2.
Exposed pad should be connected to PGND1 and PGND2.
Rev. 0 | Page 9 of 28
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