参数资料
型号: ADP5020CP-EVALZ
厂商: Analog Devices Inc
文件页数: 8/28页
文件大小: 0K
描述: BOARD EVAL PMU IMAGING ADP5020
设计资源: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
标准包装: 1
主要目的: DC/DC,LDO 步降
输出及类型: 3,非隔离
输出电压: 3.3V,1.2V,1.8V
电流 - 输出: 600mA,250mA,150mA
输入电压: 2.4 ~ 5.5 V
稳压器拓扑结构: 降压
频率 - 开关: 3MHz
板类型: 完全填充
已供物品: 2 板,CD
已用 IC / 零件: ADP5020

ADP5020
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
VDD1, VDD2, VDD3
SW1, SW2
Rating
?0.3 V to +6 V
?0.3 V to +6 V
THERMAL RESISTANCE
θ JA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 8. Thermal Resistance
VOUT1, VOUT2, VOUT3
VDD_IO
EN, SCL, SDA, SYNC, XSHTDN
?0.3 V to +6 V
?0.3V to +3.6 V
?0.3 V to V DD_IO + 0.3 V
Package Type
20-Lead LFCSP (CP-20-4)
θ JA
47.4
θ JC
4.3
Unit
°C/W
Operating Temperature Range
Thermal Data
Ambient
Junction
Storage Temperature Range
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
V ESD
Machine Model Range
Human Body Model Range
Charged Device Model
?40°C to +85°C
?40°C to +125°C
?65°C to +150°C
260°C
260°C
215°C
220°C
?200 V to +200 V
?2000 V to +2000 V
±750 V
Junction-to-ambient thermal resistance (θ JA ) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high maxi-
mum power dissipation exists, attention to thermal board design
is required. The value of θ JA may vary, depending on PCB material,
layout, and environmental conditions. The specified value of θ JA
is based on a 4-layer, 4 in × 3 in, 2 1/2 oz copper board, as per
JEDEC standards. For more information, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP) .
Stresses above those listed under Absolute Maximum Ratings
ESD CAUTION
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The ADP5020 can be damaged when the junction temperature
(T J ) limits are exceeded. Monitoring the ambient temperature
does not guarantee that T J is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated. In applications having moderate power dis-
sipation and low PCB thermal resistance, the maximum ambient
temperature can exceed the maximum limit as long as the junction
temperature is within specification limits. The T J of the device is
dependent on the ambient temperature (T A ), the power dissipation
(PD) of the device, and the junction-to-ambient thermal resistance
of the package (θ JA ). Maximum T J is calculated from T A and PD
using the following formula:
T J = T A + ( PD × θ JA )
Rev. 0 | Page 8 of 2 8
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