参数资料
型号: ADP5020CP-EVALZ
厂商: Analog Devices Inc
文件页数: 18/28页
文件大小: 0K
描述: BOARD EVAL PMU IMAGING ADP5020
设计资源: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
标准包装: 1
主要目的: DC/DC,LDO 步降
输出及类型: 3,非隔离
输出电压: 3.3V,1.2V,1.8V
电流 - 输出: 600mA,250mA,150mA
输入电压: 2.4 ~ 5.5 V
稳压器拓扑结构: 降压
频率 - 开关: 3MHz
板类型: 完全填充
已供物品: 2 板,CD
已用 IC / 零件: ADP5020
ADP5020
Activation Waveforms
VDDx
V UVLOR
POR
INTERNAL
POR
EN
I 2 C BUS
I 2 C SEQUENCER
REGISTERS
PROGRAMMING
EN_
ALL = 1
EN_
ALL = 0
t REG1
POK
BUCK 1
t REG2
POK
LDO
t REG3
POK
BUCK 2
t XSHTDN
XSHTDN
Figure 23. Regulators Are Activated by I 2 C Command
VDDx
POR
INTERNAL
POR
EN
I 2 C BUS
BUCK 1
I 2 C SEQUENCER
REGISTERS
PROGRAMMING
t REG1
POK
t REG2
POK
LDO
t REG3
POK
BUCK 2
t XSHTDN
XSHTDN
Figure 24. Activation Command Using the EN Pin
When activated through the EN pin, the sequencer is affected
only by the I 2 C commands that set or clear the regulator power
good masking bits: Bit 3 (BK1_XSHTDN), Bit 2 (BK2_XSHTDN),
and Bit 1 (LDO_XSHTDN) in the OPERATIONAL_CONTROL
register (Address 0x04). See the Default Power-On Sequence with
EN Pin section for more information. The sequence order of the
regulators is factory programmed through fuses, but the delays
between the regulators (t REG1 , t REG2 , and t REG3 ) are fixed and cannot
be changed.
The EN_ALL bit (Bit 4) in the REG_CONTROL_STATUS regi-ster
(Address 0x03) has the same functionality as the EN pin. The
sequencer has an antiglitch function that allows it to ignore supply
voltage dip if glitch time is less than 50 μs (see Figure 25).
Rev. 0 | Page 18 of 2 8
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