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参数资料
| 型号： | ADSP-21160NCB-100 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 64-BIT, 50 MHz, OTHER DSP, PBGA400 |
| 封装： | 27 X 27 MM, METRIC, PLASTIC, MS-034BAL-2, BGA-400 |
| 文件页数： | 3/60页 |
| 文件大小： | 1296K |
| 代理商： | ADSP-21160NCB-100 |
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ADSP-21160M/ADSP-21160N
Rev. B
|
Page 11 of 60
|
February 2010
PIN FUNCTION DESCRIPTIONS
ADSP-21160x pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-
tified as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST).
Tie or pull unused inputs to VDD or GND, except for the
following:
ADDR31–0, DATA63–0, PAGE, BRST, CLKOUT (ID2–0
= 00x) (Note: These pins have a logic-level hold circuit
enabled on the ADSP-21160x DSP with ID2–0 = 00x.)
PA, ACK, MS3–0, RDx, WRx, CIF, DMARx, DMAGx
(ID2–0 = 00x) (Note: These pins have a pull-up enabled on
the ADSP-21160x with ID2–0 = 00x.)
LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (Note: See
Link Port Buffer Control Register Bit definitions in the
ADSP-21160 SHARC DSP Hardware Reference.)
DTx, DRx, TCLKx, RCLKx, EMU, TMS, TRST, TDI
(Note: These pins have a pull-up.)
The following symbols appear in the Type column of Table 3:
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State (when SBTS is
asserted, or when the ADSP-21160x is a bus slave).
Table 3. Pin Function Descriptions
Pin
Type
Function
ADDR31–0
I/O/T
External Bus Address. The ADSP-21160x outputs addresses for external memory and peripherals
on these pins. In a multiprocessor system, the bus master outputs addresses for read/writes of the
internal memory or IOP registers of other ADSP-21160x DSPs. The ADSP-21160x inputs addresses
when a host processor or multiprocessing bus master is reading or writing its internal memory or
IOP registers. A keeper latch on the DSP’s ADDR31–0 pins maintains the input at the level it was
last driven (only enabled on the processor with ID2–0 = 00x).
DATA63–0
I/O/T
External Bus Data. The ADSP-21160x inputs and outputs data and instructions on these pins. Pull-
up resistors on unused DATA pins are not necessary. A keeper latch on the DSP’s DATA63-0 pins
maintains the input at the level it was last driven (only enabled on the processor with ID2–0 = 00x).
MS3–0
O/T
Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks
of external memory. Memory bank size must be defined in the SYSCON control register. The MS3–0
outputs are decoded memory address lines. In asynchronous access mode, the MS3–0 outputs
transition with the other address outputs. In synchronous access modes, the MS3–0 outputs assert
with the other address lines; however, they deassert after the first CLKIN cycle in which ACK is
sampled asserted. MS3–0 has a 20 k
Ω internal pull-up resistor that is enabled on the ADSP-21160x
with ID2–0 = 00x.
RDL
I/O/T
Memory Read Low Strobe. RDL is asserted whenever ADSP-21160x reads from the low word of
external memory or from the internal memory of other ADSP-21160x DSPs. External devices,
including other ADSP-21160x DSPs, must assert RDL for reading from the low word of processor
internal memory. In a multiprocessing system, RDL is driven by the bus master. RDL has a 20 k
Ω
internal pull-up resistor that is enabled on the processor with ID2–0 = 00x.
RDH
I/O/T
Memory Read High Strobe. RDH is asserted whenever ADSP-21160x reads from the high word of
external memory or from the internal memory of other ADSP-21160x DSPs. External devices,
including other ADSP-21160x DSPs, must assert RDH for reading from the high word of
ADSP-21160x internal memory. In a multiprocessing system, RDH is driven by the bus master.
RDH has a 20 k
Ω internal pull-up resistor that is enabled on the processor with ID2–0 = 00x.
WRL
I/O/T
Memory Write Low Strobe. WRL is asserted when ADSP-21160x writes to the low word of external
memory or internal memory of other ADSP-21160x DSPs. External devices must assert WRL for
writing to ADSP-21160x DSP’s low word of internal memory. In a multiprocessing system, WRL is
driven by the bus master. WRL has a 20 k
Ω internal pull-up resistor that is enabled on the processor
with ID2–0 = 00x.
WRH
I/O/T
Memory Write High Strobe. WRH is asserted when ADSP-21160x writes to the high word of external
memory or internal memory of other ADSP-21160x DSPs. External devices must assert WRH for
writing to ADSP-21160x DSP’s high word of internal memory. In a multiprocessing system, WRH is
driven by the bus master. WRH has a 20 k
Ω internal pull-up resistor that is enabled on the processor
with ID2–0 = 00x.
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| ADSP-21160NCB-TBD | 制造商:AD 制造商全称:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21160NCBZ-100 | 功能描述:IC DSP CONTROLLER 32BIT 400-PBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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| ADSP-21160NKB-100 | 功能描述:IC DSP CONTROLLER 32BIT 400BGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21160NKB-95 | 制造商:AD 制造商全称:Analog Devices 功能描述:DSP Microcomputer |
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