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参数资料
| 型号： | ADSP-21160NCB-100 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 64-BIT, 50 MHz, OTHER DSP, PBGA400 |
| 封装： | 27 X 27 MM, METRIC, PLASTIC, MS-034BAL-2, BGA-400 |
| 文件页数： | 5/60页 |
| 文件大小： | 1296K |
| 代理商： | ADSP-21160NCB-100 |
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ADSP-21160M/ADSP-21160N
Rev. B
|
Page 13 of 60
|
February 2010
ID2–0
I
Multiprocessing ID. Determines which multiprocessing bus request (BR1–BR6) is used by the
ADSP-21160x. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and so on. Use ID = 000
or ID = 001 in single-processor systems. These lines are a system configuration selection which
should be hardwired or only changed at reset.
DMAG1
O/T
DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21160x to indicate that the requested DMA
starts on the next cycle. Driven by bus master only. DMAG1 has a 20 k
Ω internal pull-up resistor
that is enabled on the ADSP-21160x with ID2–0 = 00x.
DMAG2
O/T
DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160x to indicate that the requested DMA
starts on the next cycle. Driven by bus master only. DMAG2 has a 20 k
Ω internal pull-up resistor
that is enabled on the ADSP-21160x with ID2–0 = 00x.
BR6–1
I/O/S
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21160x DSPs to arbitrate for bus
mastership. An ADSP-21160x only drives its own BRx line (corresponding to the value of its ID2–0
inputs) and monitors all others. In a multiprocessor system with less than six ADSP-21160x DSPs,
the unused BRx pins should be pulled high; the processor’s own BRx line must not be pulled high
or low because it is an output.
RPBA
I/S
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus
arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configu-
ration selection which must be set to the same value on every ADSP-21160x. If the value of RPBA
is changed during system operation, it must be changed in the same CLKIN cycle on every
processor.
PA
I/O/T
Priority Access. Asserting its PA pin allows an ADSP-21160x bus slave to interrupt background DMA
transfers and gain access to the external bus. PA is connected to all ADSP-21160x DSPs in the system.
If access priority is not required in a system, the PA pin should be left unconnected. PA has a 20 k
Ω
internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0 = 00x.
DTx
O
Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 k
Ω internal pull-up resistor.
DRx
I
Data Receive (Serial Ports 0, 1). Each DR pin has a 50 k
Ω internal pull-up resistor.
TCLKx
I/O
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 k
Ω internal pull-up resistor.
RCLKx
I/O
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 k
Ω internal pull-up resistor.
TFSx
I/O
Transmit Frame Sync (Serial Ports 0, 1).
RFSx
I/O
Receive Frame Sync (Serial Ports 0, 1).
LxDAT7–0
I/O
Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 k
Ω internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCTL0–1 register.
LxCLK
I/O
Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 k
Ω internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCTL0–1 register.
LxACK
I/O
Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 k
Ω internal pull-down resistor
that is enabled or disabled by the LPDRD bit of the LCOM register.
EBOOT
I
EPROM Boot Select. For a description of how this pin operates, see Table 4. This signal is a system
configuration selection that should be hardwired.
LBOOT
I
Link Boot. For a description of how this pin operates, see Table 4. This signal is a system configu-
ration selection that should be hardwired.
BMS
I/O/T
Boot Memory Select. Serves as an output or input as selected with the EBOOT and LBOOT pins; see
Table 4. This input is a system configuration selection that should be hardwired.
CLKIN
I
Local Clock In. CLKIN is the ADSP-21160x clock input. The ADSP-21160x external port cycles at the
frequency of CLKIN. The instruction cycle rate is a multiple of the CLKIN frequency; it is program-
mable at power-up. CLKIN may not be halted, changed, or operated below the specified frequency.
CLK_CFG3–0
I
Core/CLKIN Ratio Control. ADSP-21160x core clock (instruction cycle) rate is equal to n x CLKIN
where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0 inputs. For clock configuration defini-
tions, see the RESET & CLKIN section of the System Design chapter of the ADSP-21160 SHARC DSP
Hardware Reference.
Table 3. Pin Function Descriptions (Continued)
Pin
Type
Function
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21160NCB-TBD | 制造商:AD 制造商全称:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21160NCBZ-100 | 功能描述:IC DSP CONTROLLER 32BIT 400-PBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21160NCE-100 | 制造商:Analog Devices 功能描述: |
| ADSP-21160NKB-100 | 功能描述:IC DSP CONTROLLER 32BIT 400BGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21160NKB-95 | 制造商:AD 制造商全称:Analog Devices 功能描述:DSP Microcomputer |
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