参数资料
型号: ADSP-21266SKSTZ-2D
厂商: Analog Devices Inc
文件页数: 27/60页
文件大小: 0K
描述: IC DSP 32BIT 150MHZ 144-LQFP
产品培训模块: SHARC Processor Overview
标准包装: 1
系列: SHARC®
类型: 浮点
接口: DAI,SPI
时钟速率: 200MHz
非易失内存: ROM(512 kB)
芯片上RAM: 256kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-LQFP(20x20)
包装: 托盘
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Memory Write—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the processor is
accessing external memory space.
Table 22. 8-Bit Memory Write Cycle
K and B Grade
Y Grade
Parameter
Min
Min
Unit
Switching Characteristics
t ADAH
t ALEW
t ADAS 1
t ALERW
t RWALE
t WRH
1
t WW
t ADWL
t ADWH
t DWS
t DWH
t DAWH
ALE Pulse Width 2 × t PCLK – 2.0
AD15–0 Address Setup Before ALE Deasserted t PCLK – 2.8
ALE Deasserted to Write Asserted 2 × t PCLK – 3.8
Write Deasserted to ALE Asserted H + 0.5
Delay Between WR Rising Edge to Next WR Falling Edge F + H + t PCLK – 2.3
AD15–0 Address Hold After ALE Deasserted t PCLK – 0.5
WR Pulse Width D – F – 2.0
AD15–8 Address to WR Low t PCLK – 2.8
AD15–8 Address Hold After WR High H
AD7–0 Data Setup Before WR High D – F + t PCLK – 4.0
AD7–0 Data Hold After WR High H
AD15–8 Address to WR High D – F + t PCLK – 4.0
2 × t PCLK – 2.0
t PCLK – 2.8
2 × t PCLK – 3.8
H + 0.5
F + H + t PCLK – 2.3
t PCLK – 0.5
D – F – 2.0
t PCLK – 3.5
H
D – F + t PCLK – 4.0
H
D – F + t PCLK – 4.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t PCLK .
H = t PCLK (if a hold cycle is specified, else H = 0)
F = 7 × t PCLK (if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ? 9 × t PCLK .
1
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
ALE
t ALEW
t ALERW
t RWALE
t WW
WR
RD
t ADWL
t DAWH
t WRH
t ADAS
t ADAH
t ADWH
AD15 - 8
VALID
ADDRESS
VALID ADDRESS
VALID ADDRESS
t DWH
t DWS
AD7 - 0
VALID
ADDRESS
VALID DATA
VALID DATA
NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE
SHOWS ONLY TWO MEMORY WRITES TO PROVIDE THE NECESSARY TIMING INFORMATION.
Figure 19. Write Cycle for 8-Bit Memory Timing
Rev. J |
Page 27 of 60 |
July 2013
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