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参数资料
| 型号： | ADSP-21266SKSTZ-2D |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/60页 |
| 文件大小： | 0K |
| 描述： | IC DSP 32BIT 150MHZ 144-LQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，SPI |
| 时钟速率： | 200MHz |
| 非易失内存： | ROM（512 kB） |
| 芯片上RAM： | 256kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
GENERAL DESCRIPTION
The ADSP-2136x SHARC ? processor is a member of the SIMD
SHARC family of DSPs that feature Analog Devices, Inc., Super
Harvard Architecture. The processor is source code-compatible
with the ADSP-2126x and ADSP-2116x DSPs, as well as with
Table 1. Benchmarks (at 333 MHz)
first generation ADSP-2106x SHARC processors in SISD
(single-instruction, single-data) mode. The ADSP-2136x are
32-/40-bit floating-point processors optimized for high
performance automotive audio applications. They contain a
large on-chip SRAM and ROM, multiple internal buses to elim-
inate I/O bottlenecks, and an innovative digital audio interface
(DAI).
As shown in the functional block diagram on Page 1 , the
ADSP-2136x uses two computational units to deliver a signifi-
cant performance increase over the previous SHARC processors
on a range of signal processing algorithms. With its SIMD com-
putational hardware, the ADSP-2136x can perform two
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, with reversal)
FIR Filter (per tap) 1
IIR Filter (per biquad) 1
Matrix Multiply (pipelined)
[3×3] × [3×1]
[4×4] × [4×1]
Divide (y/x)
Inverse Square Root
Speed
(at 333 MHz)
27.9 μs
1.5 ns
6.0 ns
13.5 ns
23.9 ns
10.5 ns
16.3 ns
GFLOPS running at 333 MHz.
Table 2. ADSP-2136x Family Features
1
Assumes two files in multichannel SIMD mode.
Feature
RAM
ROM
Audio Decoders in ROM 1
Pulse-Width Modulation
S/PDIF
DTCP 2
SRC SNR Performance
ADSP-21362
3M bit
4M bit
No
Yes
Yes
Yes
–128 dB
ADSP-21363
3M bit
4M bit
No
Yes
No
No
No SRC
ADSP-21364
3M bit
4M bit
No
Yes
Yes
No
–140 dB
ADSP-21365
3M bit
4M bit
Yes
Yes
Yes
Yes
–128 dB
ADSP-21366
3M bit
4M bit
Yes
Yes
Yes
No
–128 dB
1
2
Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Pro Logic IIx, DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass management, delay,
speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system
configurations. Please visit www.analog.com for complete information.
The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices
sales office for more information.
The diagram on Page 1 shows the two clock domains that make
up the ADSP-2136x processors. The core clock domain contains
the following features:
? Two processing elements, each of which comprises an
ALU, multiplier, shifter, and data register file
? Data address generators (DAG1, DAG2)
? Program sequencer with instruction cache
? PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
? One periodic interval timer with pinout
? On-chip SRAM (3M bit)
? On-chip mask-programmable ROM (4M bit)
? JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user break-
points, which allow flexible exception handling.
The diagram on Page 1 also shows the following architectural
features:
? I/O processor that handles 32-bit DMA for the peripherals
? Six full duplex serial ports
? Two SPI-compatible interface ports—primary on dedi-
cated pins, secondary on DAI pins
? 8-bit or 16-bit parallel port that supports interfaces to off-
chip memory peripherals
? Digital audio interface that includes two precision clock
generators (PCG), an input data port with eight serial inter-
faces (IDP), an S/PDIF receiver/transmitter, 8-channel
asynchronous sample rate converter (ASRC), DTCP
cipher, six serial ports, a 20-bit parallel input data port
(PDAP), 10 interrupts, six flag outputs, six flag inputs,
three timers, and a flexible signal routing unit (SRU)
Rev. J |
Page 3 of 60 |
July 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21267 | 制造商:AD 制造商全称:Analog Devices 功能描述:Preliminary Technical Data |
| ADSP-21267SKBCZ-X | 制造商:AD 制造商全称:Analog Devices 功能描述:Preliminary Technical Data |
| ADSP-21267SKSTZ-X | 制造商:AD 制造商全称:Analog Devices 功能描述:Preliminary Technical Data |
| ADSP-21362 | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| adsp-21362bbc-1aa | 制造商:Analog Devices 功能描述: |
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