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| 型号： | ADSP-BF547MBBCZ-5M |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 533 MHz Blackfin Embedded Processor: ADSP-BF547MBBCZ-5M Temp Range: –40°C to +85°C Package: 400-Ball CSP_BGA BC-400-1 |
| 中文描述： | 16-BIT, 50 MHz, OTHER DSP, PBGA400 |
| 封装： | 17 X 17 MM, ROHS COMPLIANT, CSBGA-400 |
| 文件页数： | 11/100页 |
| 文件大小： | 3095K |
| 代理商： | ADSP-BF547MBBCZ-5M |
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Rev. D
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Page 18 of 100
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May 2011
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
dynamically changed without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV)
using the bfrom_SysControl() function in the on-chip ROM.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7. The default ratio is 1. This programmable core clock
capability is useful for fast core frequency modifications.
The maximum CCLK frequency not only depends on the part’s
speed grade, it also depends on the applied VDDINT voltage. See
Table 12 on Page 34 for details.
BOOTING MODES
The ADSP-BF54x Blackfin processors have many mechanisms
(listed in Table 8) for automatically loading internal and exter-
nal memory after a reset. The boot mode is specified by four
BMODE input pins dedicated to this purpose. There are two
categories of boot modes: master and slave. In master boot
modes, the processor actively loads data from parallel or serial
memories. In slave boot modes, the processor receives data
from an external host device.
The boot modes listed in Table 8 provide a number of mecha-
nisms for automatically loading the processor’s internal and
external memories after a reset. By default, all boot modes use
the slowest allowed configuration settings. Default settings can
be altered via the initialization code feature at boot time or by
proper OTP programming at pre-boot time. Some boot modes
require a boot host wait (HWAIT) signal, which is a GPIO out-
put signal that is driven and toggled by the boot kernel at boot
time. If pulled high through an external pull-up resistor, the
HWAIT signal behaves active high and will be driven low when
the processor is ready for data. Conversely, when pulled low,
HWAIT is driven high when the processor is ready for data.
When the boot sequence completes, the HWAIT pin can be
used for other purposes. By default, HWAIT functionality is on
GPIO port B (PB11). However, if PB11 is otherwise utilized in
the system, an alternate boot host wait (HWAITA) signal can be
enabled on GPIO port H (PH7) by programming the
OTP_ALTERNATE_HWAIT bit in the PBS00L OTP
memory page.
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, imple-
ment the following modes:
Idle-no boot mode (BMODE = 0x0)—In this mode, the
processor goes into the idle state. The idle boot mode helps
to recover from illegal operating modes, in case the OTP
memory is misconfigured.
Boot from 8- or 16-bit external flash memory—
(BMODE = 0x1)—In this mode, the boot kernel loads the
first block header from address 0x2000 0000 and, depend-
ing on instructions contained in the header, the boot kernel
performs an 8- or 16-bit boot or starts program execution
at the address provided by the header. By default, all con-
figuration settings are set for the slowest device possible (3-
cycle hold time; 15-cycle R/W access times; 4-cycle setup).
The ARDY pin is not enabled by default. It can, however,
be enabled by OTP programming. Similarly, all interface
behavior and timings can be customized through OTP pro-
gramming. This includes activation of burst-mode or page-
mode operation. In this mode, all asynchronous interface
signals are enabled at the port muxing level.
Table 6. Example System Clock Ratios
Signal Name
SSEL3–0
Divider Ratio
VCO/SCLK
Example Frequency Ratios
(MHz)
VCO
SCLK
0010
2:1
200
100
0110
6:1
300
50
1010
10:1
500
50
Table 7. Core Clock Ratios
Signal Name
CSEL1–0
Divider Ratio
VCO/CCLK
Example Frequency Ratios
(MHz)
VCO
CCLK
00
1:1
300
01
2:1
300
150
10
4:1
500
125
11
8:1
200
25
Table 8. Booting Modes
BMODE3– 0 Description
0000
Idle-no boot
0001
Boot from 8- or 16-bit external flash memory
0010
Boot from 16-bit asynchronous FIFO
0011
Boot from serial SPI memory (EEPROM or flash)
0100
Boot from SPI host device
0101
Boot from serial TWI memory (EEPROM or flash)
0110
Boot from TWI host
0111
Boot from UART host
1000
Reserved
1001
Reserved
1010
Boot from DDR SDRAM/Mobile DDR SDRAM
1011
Boot from OTP memory
1100
Reserved
1101
Boot from 8- or 16-bit NAND flash memory via NFC
1110
Boot from 16-bit host DMA
1111
Boot from 8-bit host DMA
Table 8. Booting Modes
(Continued)
BMODE3–0 Description
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