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| 型号： | ADSP-BF547MBBCZ-5M |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 533 MHz Blackfin Embedded Processor: ADSP-BF547MBBCZ-5M Temp Range: –40°C to +85°C Package: 400-Ball CSP_BGA BC-400-1 |
| 中文描述： | 16-BIT, 50 MHz, OTHER DSP, PBGA400 |
| 封装： | 17 X 17 MM, ROHS COMPLIANT, CSBGA-400 |
| 文件页数： | 4/100页 |
| 文件大小： | 3095K |
| 代理商： | ADSP-BF547MBBCZ-5M |
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ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. D
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Page 11 of 100
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May 2011
The timer units can be used in conjunction with the four
UARTs and the CAN controllers to measure the width of the
pulses in the data stream to provide a software auto-baud detect
function for the respective serial channels.
The timers can generate interrupts to the processor core, pro-
viding periodic events for synchronization to either the system
clock or to a count of external signals.
In addition to the general-purpose programmable timers,
another timer is also provided by the processor core. This extra
timer is clocked by the internal processor clock and is typically
used as a system tick clock for generation of periodic operating
system interrupts.
UP/DOWN COUNTER AND THUMBWHEEL
INTERFACE
A 32-bit up/down counter is provided that can sense the 2-bit
quadrature or binary codes typically emitted by industrial drives
or manual thumb wheels. The counter can also operate in
general-purpose up/down count modes. Then count direction is
either controlled by a level-sensitive input pin or by two edge
detectors.
A third input can provide flexible zero marker support and can
alternatively be used to input the push-button signal of thumb
wheels. All three pins have a programmable debouncing circuit.
An internal signal forwarded to the timer unit enables one timer
to measure the intervals between count events. Boundary regis-
ters enable auto-zero operation or simple system warning by
interrupts when programmable count values are exceeded.
SERIAL PORTS (SPORTS)
The ADSP-BF54x Blackfin processors incorporate up to four
dual-channel synchronous serial ports (SPORT0, SPORT1,
SPORT2, and SPORT3) for serial and multiprocessor commu-
nications. The SPORTs support the following features:
I2S capable operation.
Bidirectional operation. Each SPORT has two sets of inde-
pendent transmit and receive pins, enabling up to eight
channels of I2S stereo audio.
Buffered (8-deep) transmit and receive ports. Each port has
a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
Clocking. Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
Word length. Each SPORT supports serial data words from
3 to 32 bits in length, transferred most-significant-bit first
or least-significant-bit first.
Framing. Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
Companding in hardware. Each SPORT can perform
A-law or μ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
DMA operations with single-cycle overhead. Each SPORT
can receive and transmit multiple buffers of memory data
automatically. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
Interrupts. Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
Multichannel capability. Each SPORT supports 128 chan-
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The ADSP-BF54x Blackfin processors have up to three SPI-
compatible ports that allow the processor to communicate with
multiple SPI-compatible devices.
Each SPI port uses three pins for transferring data: two data pins
(master output slave input, SPIxMOSI, and master input-slave
output, SPIxMISO) and a clock pin (serial clock, SPIxSCK). An
SPI chip select input pin (SPIxSS) lets other SPI devices select
the processor, and three SPI chip select output pins per SPI port
SPIxSELy let the processor select other SPI devices. The SPI
select pins are reconfigured general-purpose I/O pins. Using
these pins, the SPI ports provide a full-duplex, synchronous
serial interface, which supports both master/slave modes and
multimaster environments.
The SPI port’s baud rate and clock phase/polarities are pro-
grammable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. The
SPI’s DMA controller can only service unidirectional accesses at
any given time.
The SPI port’s clock rate is calculated as
Where the 16-bit SPI_BAUD register contains a value of
2 to 65,535.
During transfers, the SPI port transmits and receives simultane-
ously by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
UART PORTS (UARTS)
The ADSP-BF54x Blackfin processors provide up to four full-
duplex universal asynchronous receiver/transmitter (UART)
ports. Each UART port provides a simplified UART interface to
other peripherals or hosts, supporting full-duplex, DMA-sup-
ported, asynchronous transfers of serial data. A UART port
SPI Clock Rate
f
SCLK
2
SPI_BAUD
×
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=
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| ADSP-BF547YBC-4A | 功能描述:数字信号处理器和控制器 - DSP, DSC 400MHz Blackfin Embedded Processor RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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