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参数资料
| 型号： | ADSP-BF547MBBCZ-5M |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 533 MHz Blackfin Embedded Processor: ADSP-BF547MBBCZ-5M Temp Range: –40°C to +85°C Package: 400-Ball CSP_BGA BC-400-1 |
| 中文描述： | 16-BIT, 50 MHz, OTHER DSP, PBGA400 |
| 封装： | 17 X 17 MM, ROHS COMPLIANT, CSBGA-400 |
| 文件页数： | 12/100页 |
| 文件大小： | 3095K |
| 代理商： | ADSP-BF547MBBCZ-5M |
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ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. D
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Page 19 of 100
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May 2011
Boot from 16-bit asynchronous FIFO (BMODE = 0x2)—In
this mode, the boot kernel starts booting from address
0x2030 0000. Every 16-bit word that the boot kernel has to
read from the FIFO must be requested by a low pulse on
the DMAR1 pin.
Boot from serial SPI memory, EEPROM or flash
(BMODE = 0x3)—8-, 16-, 24- or 32-bit addressable devices
are supported. The processor uses the PE4 GPIO pin to
select a single SPI EEPROM or flash device and uses SPI0
to submit a read command and successive address bytes
(0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device
is detected. Pull-up resistors are required on the SPI0SEL1
and SPI0MISO pins. By default, a value of 0x85 is written to
the SPI0_BAUD register.
Boot from SPI host device (BMODE = 0x4)—The proces-
sor operates in SPI slave mode (using SPI0) and is
configured to receive the bytes of the .LDR file from an SPI
host (master) agent. The HWAIT signal must be interro-
gated by the host before every transmitted byte. A pull-up
resistor is required on the SPI0SS input. A pull-down resis-
tor on the serial clock (SPI0SCK) may improve signal
quality and booting robustness.
Boot from serial TWI memory, EEPROM or flash
(BMODE = 0x5)—The processor operates in master mode
(using TWI0) and selects the TWI slave with the unique ID
0xA0. The processor submits successive read commands to
the memory device starting at two-byte internal address
0x0000 and begins clocking data into the processor. The
TWI memory device should comply with Philips I2C Bus
Specification version 2.1 and have the capability to auto-
increment its internal address counter such that the con-
tents of the memory device can be read sequentially. By
default, a prescale value of 0xA and CLKDIV value of
0x0811 is used. Unless altered by OTP settings, an I2C
memory that takes two address bytes is assumed. Develop-
ment tools ensure that data that is booted to memories that
cannot be accessed by the Blackfin core is written to an
intermediate storage place and then copied to the final des-
tination via memory DMA.
Boot from TWI host (BMODE = 0x6)—The TWI host
agent selects the slave with the unique ID 0x5F. The proces-
sor (using TWI0) replies with an acknowledgement, and
the host can then download the boot stream. The TWI host
agent should comply with Philips I2C Bus Specification ver-
sion 2.1. An I2C multiplexer can be used to select one
processor at a time when booting multiple processors from
a single TWI.
Boot from UART host (BMODE = 0x7)—In this mode, the
processor uses UART1 as the booting source. Using an
autobaud handshake sequence, a boot-stream-formatted
program is downloaded by the host. The host agent selects
a bit rate within the UART’s clocking capabilities.
When performing the autobaud, the UART expects an “@”
(0x40) character (eight data bits, one start bit, one stop bit,
no parity bit) on the UART1RX pin to determine the bit
rate. It then replies with an acknowledgement, which is
composed of four bytes (0xBF, the value of UART1_DLL,
the value of UART1_DLH, and finally 0x00). The host can
then download the boot stream. The processor deasserts
the UART1RTS output to hold off the host; UART1CTS
functionality is not enabled at boot time.
Boot from (DDR) SDRAM (BMODE = 0xA)—In this
mode, the boot kernel starts booting from address
0x0000 0010. This is a warm boot scenario only. The
SDRAM is expected to contain a valid boot stream and the
SDRAM controller must have been configured by the OTP
settings.
Boot from 8-bit and 16-bit external NAND flash memory
(BMODE = 0xD)—In this mode, auto detection of the
NAND flash device is performed. The processor configures
PORTJ GPIO pins PJ1 and PJ2 to enable the ND_CE and
ND_RB signals, respectively. For correct device operation,
pull-up resistors are required on both ND_CE (PJ1) and
ND_RB (PJ2) signals. By default, a value of 0x0033 is writ-
ten to the NFC_CTL register. The booting procedure
always starts by booting from byte 0 of block 0 of the
NAND flash device. In this boot mode, the HWAIT signal
does not toggle. The respective GPIO pin remains in the
high-impedance state.
NAND flash boot supports the following features:
Device auto detection
Error detection and correction for maximum
reliability
No boot stream size limitation
Peripheral DMA via channel 22, providing efficient
transfer of all data (excluding the ECC parity data)
Software-configurable boot mode for booting from
boot streams expanding multiple blocks, including
bad blocks
Software-configurable boot mode for booting from
multiple copies of the boot stream allowing for han-
dling of bad blocks and uncorrectable errors
Configurable timing via OTP memory
Small page NAND flash devices must have a 512-byte page
size, 32 pages per block, a 16-byte spare area size and a bus
configuration of eight bits. By default, all read requests
from the NAND flash are followed by four address cycles.
If the NAND flash device requires only three address
cycles, then the device must be capable of ignoring the
additional address cycle.
The small page NAND flash device must comply with the
following command set:
Reset: 0xFF
Read lower half of page: 0x00
Read upper half of page: 0x01
Read spare area: 0x50
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| ADSP-BF547YBC-4A | 功能描述:数字信号处理器和控制器 - DSP, DSC 400MHz Blackfin Embedded Processor RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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