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参数资料
| 型号： | ADSP-BF547MBBCZ-5M |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 533 MHz Blackfin Embedded Processor: ADSP-BF547MBBCZ-5M Temp Range: –40°C to +85°C Package: 400-Ball CSP_BGA BC-400-1 |
| 中文描述： | 16-BIT, 50 MHz, OTHER DSP, PBGA400 |
| 封装： | 17 X 17 MM, ROHS COMPLIANT, CSBGA-400 |
| 文件页数： | 5/100页 |
| 文件大小： | 3095K |
| 代理商： | ADSP-BF547MBBCZ-5M |
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Rev. D
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Page 12 of 100
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May 2011
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
includes support for five to eight data bits, one or two stop bits,
and none, even, or odd parity. Each UART port supports two
modes of operation:
PIO (programmed I/O). The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
DMA (direct memory access). The DMA controller trans-
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates. Flexi-
ble interrupt timing options are available on the transmit
side.
Each UART port’s baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
Supporting bit rates ranging from (fSCLK/1,048,576) to
(fSCLK) bits per second.
Supporting data formats from seven to 12 bits per frame.
Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as
Where the 16-bit UART divisor comes from the UARTx_DLH
register (most significant 8 bits) and UARTx_DLL register (least
significant eight bits), and the EDBO is a bit in the
UARTx_GCTL register.
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
UART1 and UART3 feature a pair of UARTxRTS (request to
send) and UARTxCTS (clear to send) signals for hardware flow
purposes. The transmitter hardware is automatically prevented
from sending further data when the UARTxCTS input is de-
asserted. The receiver can automatically de-assert its
UARTxRTS output when the enhanced receive FIFO exceeds a
certain high-water level. The capabilities of the UARTs are fur-
ther extended with support for the Infrared Data Association
(IrDA) Serial Infrared Physical Layer Link Specification (SIR)
protocol.
CONTROLLER AREA NETWORK (CAN)
The ADSP-BF54x Blackfin processors offer up to two CAN con-
trollers that are communication controllers that implement the
controller area network (CAN) 2.0B (active) protocol. This pro-
tocol is an asynchronous communications protocol used in both
industrial and automotive control systems. The CAN protocol is
well suited for control applications due to its capability to com-
municate reliably over a network since the protocol
incorporates CRC checking, message error tracking, and fault
node confinement.
The ADSP-BF54x Blackfin processors’ CAN controllers offer
the following features:
32 mailboxes (8 receive only, 8 transmit only, 16 configu-
rable for receive or transmit).
Dedicated acceptance masks for each mailbox.
Additional data filtering on first two bytes.
Support for both the standard (11-bit) and extended (29-
bit) identifier (ID) message formats.
Support for remote frames.
Active or passive network support.
CAN wakeup from hibernation mode (lowest static power
consumption mode).
Interrupts, including: TX complete, RX complete, error
and global.
The electrical characteristics of each network connection are
very demanding, so the CAN interface is typically divided into
two parts: a controller and a transceiver. This allows a single
controller to support different drivers and CAN networks. The
ADSP-BF54x Blackfin processors’ CAN module represents only
the controller part of the interface. The controller interface sup-
ports connection to 3.3 V high speed, fault-tolerant, single-wire
transceivers.
An additional crystal is not required to supply the CAN clock, as
the CAN clock is derived from the processor system clock
(SCLK) through a programmable divider.
TWI CONTROLLER INTERFACE
The ADSP-BF54x Blackfin processors include up to two 2-wire
interface (TWI) modules for providing a simple exchange
method of control data between multiple devices. The modules
are compatible with the widely used I2C bus standard. The TWI
modules offer the capabilities of simultaneous master and slave
operation and support for both 7-bit addressing and multime-
dia data arbitration. Each TWI interface uses two pins for
transferring clock (SCLx) and data (SDAx), and supports the
protocol at speeds up to 400K bits/sec. The TWI interface pins
are compatible with 5 V logic levels.
Additionally, the ADSP-BF54x Blackfin processors’ TWI mod-
ules are fully compatible with serial camera control bus (SCCB)
functionality for easier control of various CMOS camera sensor
devices.
PORTS
Because of their rich set of peripherals, the ADSP-BF54x
Blackfin processors group the many peripheral signals to ten
ports—referred to as Port A to Port J. Most ports contain 16
pins, though some have fewer. Many of the associated pins are
shared by multiple signals. The ports function as multiplexer
controls. Every port has its own set of memory-mapped regis-
ters to control port muxing and GPIO functionality.
UART Clock Rate
f
SCLK
16
1EDBO
–
()
UART_Divisor
×
------------------------------------------------------------------------------
=
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| ADSP-BF547YBC-4A | 功能描述:数字信号处理器和控制器 - DSP, DSC 400MHz Blackfin Embedded Processor RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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