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| 型号： | ADSP-BF547MBBCZ-5M |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 533 MHz Blackfin Embedded Processor: ADSP-BF547MBBCZ-5M Temp Range: –40°C to +85°C Package: 400-Ball CSP_BGA BC-400-1 |
| 中文描述： | 16-BIT, 50 MHz, OTHER DSP, PBGA400 |
| 封装： | 17 X 17 MM, ROHS COMPLIANT, CSBGA-400 |
| 文件页数： | 79/100页 |
| 文件大小： | 3095K |
| 代理商： | ADSP-BF547MBBCZ-5M |
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Rev. D
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Page 8 of 100
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May 2011
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
The controller provides support for five different types of
events:
Emulation. An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
Reset. This event resets the processor.
Non-maskable interrupt (NMI). The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
Exceptions. Events that occur synchronously to program
flow (that is, the exception is taken before the instruction is
allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
Interrupts. Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The ADSP-BF54x Blackfin processor event controller consists
of two stages, the core event controller (CEC) and the system
interrupt controller (SIC). The core event controller works with
the system interrupt controller to prioritize and control all sys-
tem events. Conceptually, interrupts from the peripherals enter
into the SIC and are then routed directly into the general-pur-
pose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF54x Blackfin processors.
Table 3 describes the inputs to the CEC, identifies their names
in the event vector table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and rout-
ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF54x Blackfin processors provide a
default mapping, the user can alter the mappings and priorities
of interrupt events by writing the appropriate values into the
interrupt assignment registers (SIC_IARx). The ADSP-BF54x
Hardware Reference Manual, “System Interrupts” chapter
describes the inputs into the SIC and the default mappings into
the CEC.
Event Control
The ADSP-BF54x Blackfin processors provide the user with a
very flexible mechanism to control the processing of events. In
the CEC, three registers are used to coordinate and control
events. Each register is 16 bits wide:
CEC interrupt latch register (ILAT). The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may be written only when its corresponding IMASK bit
is cleared.
CEC interrupt mask register (IMASK). The IMASK regis-
ter controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and is processed by the CEC when asserted. A
cleared bit in the IMASK register masks the event, prevent-
ing the processor from servicing the event even though the
event may be latched in the ILAT register. This register
may be read or written while in supervisor mode. Note that
general-purpose interrupts can be globally enabled and dis-
abled with the STI and CLI instructions, respectively.
CEC interrupt pending register (IPEND). The IPEND reg-
ister keeps track of all nested events. A set bit in the IPEND
register indicates that the event is currently active or nested
at some level. This register is updated automatically by the
controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in the ADSP-BF54x Hardware Reference Manual,
“System Interrupts” chapter.
Table 3. Core Event Controller (CEC)
Priority
(0 is Highest)
Event Class
EVT Entry
0Emulation/Test Control
EMU
1
Reset
RST
2
Nonmaskable Interrupt
NMI
3Exception
EVX
4
Reserved
—
5
Hardware Error
IVHW
6
Core Timer
IVTMR
7
General Interrupt 7
IVG7
8
General Interrupt 8
IVG8
9
General Interrupt 9
IVG9
10
General Interrupt 10
IVG10
11
General Interrupt 11
IVG11
12
General Interrupt 12
IVG12
13
General Interrupt 13
IVG13
14
General Interrupt 14
IVG14
15
General Interrupt 15
IVG15
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