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参数资料
型号： ADSP-BF547MBBCZ-5M
厂商： ANALOG DEVICES INC
元件分类： 数字信号处理
英文描述： 533 MHz Blackfin Embedded Processor: ADSP-BF547MBBCZ-5M Temp Range: –40°C to +85°C Package: 400-Ball CSP_BGA BC-400-1
中文描述： 16-BIT, 50 MHz, OTHER DSP, PBGA400
封装： 17 X 17 MM, ROHS COMPLIANT, CSBGA-400
文件页数： 8/100页
文件大小： 3095K
代理商： ADSP-BF547MBBCZ-5M
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. D
|
Page 15 of 100
|
May 2011
Interrupts are generated when a user-defined amount of syn-
chronous data has been sent or received by the processor or
when asynchronous packets or control messages have been sent
or received.
The MXVR peripheral can wake up the ADSP-BF549 Blackfin
processor from sleep mode when a wakeup preamble is received
over the network or based on any other MXVR interrupt event.
Additionally, detection of network activity by the MXVR can be
used to wake up the ADSP-BF549 Blackfin processor from the
hibernate state. These features allow the ADSP-BF549 processor
to operate in a low-power state when there is no network activ-
ity or when data is not currently being received or transmitted
by the MXVR.
The MXVR clock is provided through a dedicated external crys-
tal or crystal oscillator. The frequency of the external crystal or
crystal oscillator can be 256 Fs, 384 Fs, 512 Fs, or 1024 Fs for
Fs = 38 kHz, 44.1 kHz, or 48 kHz. If using a crystal to provide
the MXVR clock, use a parallel-resonant, fundamental mode,
microprocessor-grade crystal.
DYNAMIC POWER MANAGEMENT
The ADSP-BF54x Blackfin processors provide five operating
modes, each with a different performance/power profile. In
addition, dynamic power management provides the control
functions to dynamically alter the processor core supply voltage,
further reducing power dissipation. Control of clocking to each
of the ADSP-BF54x Blackfin processors’ peripherals also
reduces power consumption. See Table 4 for a summary of the
power settings for each mode.
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing the capability to run at the maximum operational fre-
quency. This is the power-up default execution state in which
maximum performance can be achieved. The processor core
and all enabled peripherals run at full speed.
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. DMA
access is available to appropriately configured L1 memories.
In the active mode, it is possible to disable the control input to
the PLL by setting the PLL_OFF bit in the PLL control register.
This register can be accessed with a user-callable routine in the
on-chip ROM called bfrom_SysControl(). For more informa-
tion, see the “Dynamic Power Management” chapter in the
ADSP-BF54x Blackfin Processor Hardware Reference. If dis-
abled, the PLL must be re-enabled before transitioning to the
full-on or sleep modes.
Figure 5. MXVR MOST Connection
600Z
MLF_M
MOST
NETWORK
AUDIO
CHANNELS
GNDMP
VDDMP
MOST FOT
TXVCC
TX_DATA
RX_DATA
STATUS
AUDIO DAC
27
R1
330
C1
0.047 F
0.1 F
0.01 F
C2
330pF
ADSP-BF549
MXI
MXO
MLF_P
PG11/
MTXON
PH5/MTX
PH6/MRX
PH7/
MRXON
PC1/MMCLK
MFS
PC5/MBCLK
PC3/TSCLK0
PC7/RSCLK0
PC4/RFS0
PC2/DT0PRI
SDATA
L/RCLK
BCLK
MCLK
33
1.25V
GND
VDDINT
1%
2% PPS
0
TXGND
5.0V
RXVCC
RXGND
600Z
10k
24.576MHz
XN4114
Table 4. Power Settings
Mode/S
ta
te
PLL
Bypassed
Co
re
Clock
(C
C
L
K
)
Sy
st
e
m
Clock
(SC
L
K
)
Co
re
Po
w
e
r
Full On
Enabled
No
Enabled
On
Active
Enabled/
Disabled
Yes
Enabled
On
Sleep
Enabled
-
Disabled
Enabled
On
Deep Sleep
Disabled
-
Disabled
On
Hibernate
Disabled
-
Disabled
Off
相关PDF资料
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