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| 型号： | ADSP-BF547MBBCZ-5M |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 533 MHz Blackfin Embedded Processor: ADSP-BF547MBBCZ-5M Temp Range: –40°C to +85°C Package: 400-Ball CSP_BGA BC-400-1 |
| 中文描述： | 16-BIT, 50 MHz, OTHER DSP, PBGA400 |
| 封装： | 17 X 17 MM, ROHS COMPLIANT, CSBGA-400 |
| 文件页数： | 9/100页 |
| 文件大小： | 3095K |
| 代理商： | ADSP-BF547MBBCZ-5M |
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Rev. D
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Page 16 of 100
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May 2011
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity will wake up the
processor. In the sleep mode, assertion of a wakeup event
enabled in the SIC_IWRx register causes the processor to sense
the value of the BYPASS bit in the PLL control register
(PLL_CTL). If BYPASS is disabled, the processor transitions to
the full on mode. If BYPASS is enabled, the processor transi-
tions to the active mode.
In the sleep mode, system DMA access to L1 memory is not
supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but will not be able to
access internal resources or external memory. This
powered-down mode can only be exited by assertion of the reset
interrupt (RESET) or by an asynchronous interrupt generated
by the RTC. In deep sleep mode, an asynchronous RTC inter-
rupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the proces-
sor to transition to the full on mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regu-
lator for the processor can be shut off by using the
bfrom_SysControl() function in the on-chip ROM. This sets the
internal power supply voltage (VDDINT) to 0 V to provide the
greatest power savings mode. Any critical information stored
internally (memory contents, register contents, and so on) must
be written to a non-volatile storage device prior to removing
power if the processor state is to be preserved.
Since VDDEXT is still supplied in this mode, all of the external
pins three-state, unless otherwise specified. This allows other
devices that may be connected to the processor to have power
still applied without drawing unwanted current.
The internal supply regulator can be woken up by CAN, by the
MXVR, by the keypad, by the up/down counter, by the USB,
and by some GPIO pins. It can also be woken up by a real-time
clock wakeup event or by asserting the RESET pin. Waking up
from hibernate state initiates the hardware reset sequence.
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in hibernate
state. State variables may be held in external SRAM or DDR
memory.
Power Domains
As shown in Table 5, the ADSP-BF54x Blackfin processors sup-
port different power domains. The use of multiple power
domains maximizes flexibility while maintaining compliance
with industry standards and conventions. By isolating the inter-
nal logic of the ADSP-BF54x Blackfin processors into its own
power domain separate from the RTC and other I/O, the pro-
cessors can take advantage of dynamic power management
without affecting the RTC or other I/O devices. There are no
sequencing requirements for the various power domains.
VOLTAGE REGULATION
The ADSP-BF54x Blackfin processors provide an on-chip volt-
age regulator that can generate processor core voltage levels
from an external supply (see specifications in Operating Condi-
tions on Page 33). Figure 6 on Page 17 shows the typical
external components required to complete the power manage-
ment system. The regulator controls the internal logic voltage
levels and is programmable with the voltage regulator control
register (VR_CTL) in increments of 50 mV. This register can be
accessed using the bfrom_SysControl() function in the on-chip
ROM. To reduce standby power consumption, the internal volt-
age regulator can be programmed to remove power to the
processor core while keeping I/O power supplied. While in
hibernate state, VDDEXT, VDDRTC, VDDDDR, VDDUSB, and VDDVR can
still be applied, eliminating the need for external buffers. The
voltage regulator can be activated from this power-down state
by assertion of the RESET pin, which then initiates a boot
sequence. The regulator can also be disabled and bypassed at the
user’s discretion. For all 600 MHz speed grade models and all
automotive grade models, the internal voltage regulator must
not be used and VDDVR must be tied to VDDEXT. For additional
information regarding design of the voltage regulator circuit,
see Switching Regulator Design Considerations for the ADSP-
BF533 Blackfin Processors (EE-228).
Table 5. Power Domains
Power Domain
VDD Range
All internal logic, except RTC, DDR, and USB
VDDINT
RTC internal logic and crystal I/O
VDDRTC
DDR external memory supply
VDDDDR
USB internal logic and crystal I/O
VDDUSB
Internal voltage regulator
VDDVR
MXVR PLL and logic
VDDMP
All other I/O
VDDEXT
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