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| 型号： | ADUC7128BSTZ126-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 65/92页 |
| 文件大小： | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 64-LQFP |
| 产品培训模块： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | PLA，POR，PWM，PSM，温度传感器，WDT |
| 输入/输出数： | 28 |
| 程序存储器容量： | 126KB（63K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 10x12b; D/A 1x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 64-LQFP |
| 包装： | 标准包装 |
| 配用： | EVAL-ADUC7128QSPZ-ND - KIT DEV FOR ADUC7128 |
| 其它名称： | ADUC7128BSTZ126-RLDKR |
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ADuC7128/ADuC7129
Rev. 0 | Page 68 of 92
Bit
Description
7
Master Serial Clock Enable Bit.
Set by user to enable generation of the serial clock in master mode.
Cleared by user to disable serial clock in master mode.
6
Loop-Back Enable Bit.
Set by user to internally connect the transition to the reception to test user software.
Cleared by user to operate in normal mode.
5
Start Back-Off Disable Bit.
Set by user in multimaster mode. If losing arbitration, the master immediately tries to retransmit.
Cleared by user to enable start back-off. After losing arbitration, the master waits before trying to retransmit.
4
Hardware General Call Enable. When this bit and Bit 3 are set, and have received a general call (Address 0x00) and a data byte, the
device checks the contents of the I2C0ALT against the receive register. If the contents match, the device has received a hardware
general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to.
This is a “to whom it may concern” call. The ADuC7128/ADuC7129 watch for these addresses. The device that requires attention
embeds its own address into the message. All masters listen and the one that can handle the device contacts its slave and acts
appropriately. The LSB of the I2C0ALT register should always be written to a 1, as per the I2C January 2000 specification.
3
General Call Enable Bit.
Set this bit to enable the slave device to acknowledge an I2C general call, Address 0x00 (write). The device then recognizes a data
bit. If it receives a 0x06 (reset and write programmable part of slave address by hardware) as the data byte, the I2C interface resets as per
the I2C January 2000 specification. This command can be used to reset an entire I2C system. The general call interrupt status bit
sets on any general call. The user must take corrective action by setting up the I2C interface after a reset. If it receives a 0x04
(write programmable part of slave address by hardware) as the data byte, the general call interrupt status bit sets on any general
call. The user must take corrective action by reprogramming the device address.
2
Reserved.
1
Master Enable Bit.
Set by user to enable the master I2C channel.
Cleared by user to disable the master I2C channel.
0
Slave Enable Bit.
Set by user to enable the slave I2C channel. A slave transfer sequence is monitored for the device address in I2C0ID0, I2C0ID1,
I2C0ID2, and I2C0ID3. If the device address is recognized, the part participates in the slave transfer sequence.
Cleared by user to disable the slave I2C channel.
I2CxDIV Register
Name
Address
Default Value
Access
I2C0DIV
0xFFFF0830
0x1F1F
R/W
I2C1DIV
0xFFFF0930
0x1F1F
R/W
I2CxDIV are the clock divider registers.
I2CxIDx Register
Name
Address
Default Value
Access
I2C0ID0
0xFFFF0838
0x00
R/W
I2C0ID1
0xFFFF083C
0x00
R/W
I2C0ID2
0xFFFF0840
0x00
R/W
I2C0ID3
0xFFFF0844
0x00
R/W
I2C1ID0
0xFFFF0938
0x00
R/W
I2C1ID1
0xFFFF093C
0x00
R/W
I2C1ID2
0xFFFF0940
0x00
R/W
I2C1ID3
0xFFFF0944
0x00
R/W
I2CxID0, I2CxID1, I2CxID2, and I2CxID3 are slave address
device ID registers of I2Cx.
I2CxSSC Register
Name
Address
Default Value
Access
I2C0SSC
0xFFFF0848
0x01
R/W
I2C1SSC
0xFFFF0948
0x01
R/W
I2CxSSC is an 8-bit start/stop generation counter. It holds off
SDA low for start and stop conditions.
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相关代理商/技术参数 |
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|---|---|
| ADUC7128BSTZ126-RL2 | 制造商:AD 制造商全称:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC |
| ADUC7129 | 制造商:AD 制造商全称:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC |
| ADUC7129BSTZ126 | 功能描述:IC DAS MCU ARM7 ADC/DDS 80-LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 标准包装:38 系列:Encore!® XP® 核心处理器:eZ8 芯体尺寸:8-位 速度:5MHz 连通性:IrDA，UART/USART 外围设备:欠压检测/复位，LED，POR，PWM，WDT 输入/输出数:16 程序存储器容量:4KB（4K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:1K x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 3.6 V 数据转换器:- 振荡器型:内部 工作温度:-40°C ~ 105°C 封装/外壳:20-SOIC（0.295"，7.50mm 宽） 包装:管件 其它名称:269-4116Z8F0413SH005EG-ND |
| ADUC7129BSTZ1262 | 制造商:AD 制造商全称:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC |
| ADUC7129BSTZ126-RL | 功能描述:IC DAS MCU ARM7 ADC/DDS 80-LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 产品培训模块:Graphics LCD System and PIC24 Interface Asynchronous Stimulus 标准包装:27 系列:PIC® 24H 核心处理器:PIC 芯体尺寸:16-位 速度:40 MIP 连通性:I²C，SPI，UART/USART 外围设备:欠压检测/复位，POR，PWM，WDT 输入/输出数:21 程序存储器容量:12KB（4K x 24） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:1K x 8 电压 - 电源 (Vcc/Vdd):3 V ~ 3.6 V 数据转换器:A/D 10x10b/12b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 包装:管件 产品目录页面:648 (CN2011-ZH PDF) 配用:AC164339-ND - MODULE SKT FOR PM3 28SOICDV164033-ND - KIT START EXPLORER 16 MPLAB ICD2 |
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