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| 型号： | AN-136 |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | A NEW GENERATION OF TAG SRAMS?THE IDT71215 AND |
| 中文描述： | 作为TAG SRAM的呢？IDT71215和新一代 |
| 文件页数： | 3/12页 |
| 文件大小： | 103K |
| 代理商： | AN-136 |
3
A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216
APPLICATION NOTE AN-136
Figure 3. Simplified 71215 / 71216 Block Diagram (71216 signal names are in parenthesis)
For a 1MB cache and 4GB of cacheable main memory, two
of the devices may be cascaded in depth without any timing
penalty apart from increased capacitive loading. This is
accomplished with the two Chip Select pins. A low order
address signal may be connected to
CS1
on one chip and to
CS2 on the other so that at any given time, one is selected and
the other is deselected. The deselected chip ignores all
control inputs (except
RESET
and
PWRDN
) and tri-states its
outputs so that the two chips can be conveniently bussed
together. As expected, worst case timing delays from the Chip
Select inputs are the same as for the Address inputs. When
only a single 71215 or 71216 is used in an application,
CS1
is
tied to V
SS
and CS2 is tied to V
CC
.
With a 16K x 12 tag memory, the 71215 and 71216 are
wider and deeper than most Tag RAMs. For a typical 64-bit
CPU with a 32-byte line size, the 16K depth supports a 512KB
cache while the 12-bit tag field supports 2GB of cacheable
main memory. Thus, only a single component is required for
most applications. Table 1 shows the relationships between
Tag RAM size, cache size, and cacheable main memory size.
The Tag depth is equal to the cache size divided by the line
size. The Tag width is equal to the base-2 log of the ratio of
main memory size to cache size.
TABLE 1: REQUIRED TAG RAM SIZE AS A
FUNCTION OF CACHE SIZE AND MAIN
MEMORY SIZE
(For 32-byte line size and direct
mapped cache architecture.)
Cache Size
Cacheable Main Memory Size
256MB
1GB
4K x 11
4K x 13
8K x 10
8K x 12
16K x 9
16K x 11 16K x 12 16K x 13
32K x 8
32K x 10 32K x 11 32K x 12
64MB
4K x 9
8K x 8
16K x 7
32K x 6
2GB
4K x 14
8K x 13
4GB
4K x 15
8K x 14
128KB
256KB
512KB
1MB
3176 tbl 01
CLK
CS2
BRDYH (TAH)
W/
R
(TT1)
MATCH
SFUNC
ADDR(0:13)
VLDin / S1
IN
DLYin / S2
IN
WTin / S3
IN
BRDYIN
(TAIN)
VLD
OUT
DLY
OUT
WT
OUT
CS1
PWRDN
BRDYOE (TAOE)
WET
WES
BRDY
(
TA
)
R
16K x 12
MEMORY
TAG (0:11)
OET
16K x 3
MEMORY
MATCH AND
BRDY LOGIC
Chip enabling
Reseting the 16K x 3 memory
Powering down
Disabling outputs
CONTROL
LOGIC
OES
RESET
3176 drw 03
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