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| 型号： | AN-136 |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | A NEW GENERATION OF TAG SRAMS?THE IDT71215 AND |
| 中文描述： | 作为TAG SRAM的呢？IDT71215和新一代 |
| 文件页数： | 6/12页 |
| 文件大小： | 103K |
| 代理商： | AN-136 |
6
A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216
APPLICATION NOTE AN-136
Figure 6. Generic Mode Logic (71216 pin names are in parenthesis)
The status bits are accessed through separate input pins
and output pins. This avoids the need for fast turn around on
this bus as in the following example: a single word write hit to
a write back line results in the need to set the state to dirty (also
called “modified”). The status memory must go from reading
to writing then back to reading in as little as two cycles. If
common I/O is preferred, the user may tie the respective input
and output pins together. The status memory control signals
(
WES
and
OES
) are equivalent to
WET
and
OET
for the tag
memory. Also, because the status field is separate I/O,
OES
is normally tied to V
SS
to permanently enable the status
outputs.
The tag and status memories are controlled independently
since normal operation of the 71215/16 finds the tag memory
in match mode and the status memory in read mode. Often,
however,
WET
and
WES
are tied together in a design because
the write function tends to be common between them. For
those times when only the status bits need to be updated,
WET
,
WES
and
OET
can be asserted together without having
to externally drive the TAG bus. This causes the data read
from the tag field to be written back to the same address,
resulting in no change to the tag data.
Note that there is only one address register that is used by
both memory segments. The address is registered when
either
WET
or
WES
is sampled low, and is flow-through when
both
WET
and
WES
are sampled high.
The entire status memory is cleared to zeros when
RESET
is sampled low on at least one rising edge of CLK. This can
be used to put the cache into a known state after power up, or
after a cache flush. Since reset is a type of write,
WET
and
WES
are required to be high during reset.
PWRDN
must also
be high, but the state of the chip select inputs does not matter.
During reset,
BRDY
/
TA
is driven high, and MATCH is driven
low.
MATCH,
BRDY
As mentioned earlier, the 71215/16 is in match mode when
OET
is high and
WET
is sampled high. This allows the TAG0
AND
TA
TAG
ADDRESS
V
D
WP
MATCH
BRDYH (TAH)
BRDYOE
(
TAOE
)
COMPARE
MEMORY
BRDY and Match logic (Generic Status bit mode)
TA names added for ap note
WT
IN
/ S3
IN
DTY
IN
/ S2
IN
VLD
IN
/ S1
IN
WT
OUT
/ S3
OUT
DTY
OUT
/ S2
OUT
VLD
OUT
/ S1
OUT
BRDY
(
TA
)
CLK
WES
WET
internal RESET
OE
BRDYIN
(
TAIN
)
3176 drw 06
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