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| 型号： | AN-136 |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | A NEW GENERATION OF TAG SRAMS?THE IDT71215 AND |
| 中文描述： | 作为TAG SRAM的呢？IDT71215和新一代 |
| 文件页数： | 7/12页 |
| 文件大小： | 103K |
| 代理商： | AN-136 |
7
A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216
APPLICATION NOTE AN-136
- TAG11 inputs (high order bits of the CPU/system address
bus) to be compared with internally stored data. When
SFUNC is low, the stored VLD bit is combined with this
comparator output to generate a MATCH output that is true
only when both the tag comparison is true and the VLD bit is
high. Thus, an invalid tag entry does not generate a hit. Note
that
OES
and
WES
do not affect internal access of the status
bits. When SFUNC is high, the status bits are generic and
MATCH is simply the output of the comparator. MATCH is
driven low when the 71215/16 is not in match mode. When the
chip is deselected, MATCH becomes high impedance.
The cache/memory controller has traditionally generated
the
BRDY
/
TA
signal to the CPU, using MATCH and other
inputs. This is a critical timing path. During a zero-wait-state
lead-off, there are only two clock cycles for the CPU to drive
the address and other bus signals, and for
BRDY
or
TA
to be
returned to the CPU by the cache controller. See Figure 7.
Typically there is not enough time to have two chips (Tag RAM
and controller) in this timing path. The 71215/16 address this
difficulty by incorporating logic for generating
BRDY
/
TA
, thereby
removing the cache controller from this path. This is shown in
Figure 8.
While the cache controller is removed from the primary
BRDY
/
TA
timing path, it must still play a part in generating
BRDY
/
TA
. The controller has address and other bus cycle
information that is needed to qualify the generation of
BRDY
/
TA
. This qualification logic is best placed in parallel with the
tag lookup, rather than in series with it. Also, there are cases
where the the generation of
BRDY
/
TA
by the 71215/16 must
be blocked so that the cache/memory controller can generate
it instead.
Logic has been included in the 71215/16 that enables it to
qualify
BRDY
/
TA
for one particular case. While a write hit to
a write-back line can be handled by the cache alone, a write-
through line requires that the write also proceed to main
memory. In the former case the cache can respond without
wait states and
BRDY
/
TA
is driven low immediately as the
result of a tag match and set VLD bit. In the latter case, main
memory writes normally require wait states. If a line (or the
whole cache) is write-through, the 71215/16 should not drive
BRDY
/
TA
low, so that the cache/memory controller may do so
later when the main memory (or write buffer) write is complete.
When the Tag RAM is in dedicated status mode (SFUNC low),
the stored WT bit determines whether the line is write-through
(high) or write-back (low). Note that it may also be used to
denote a write protected line. Another pin - W/
R
and TT1 on
the 71215 and 71216 respectively - connects directly to the
CPU for distinguishing between processor reads and proces-
sor writes. These two bits of information are used to block
internal generation of
BRDY
/
TA
during a processor write to a
write-through line. Without this feature, the cache controller
might not have enough time to generate a blocking signal (as
described below) based on the WT output from the Tag RAM.
If a user wants to gate the VLD bit with MATCH but not use the
WT bit in combination with W/
R
or TT1, he should select the
dedicated mode (SFUNC low) and tie W/R low or TT1 high.
Note that the one functional difference between the 71215 and
71216 is the polarity of the W/
R
and TT1 signals.
The cache controller may have additional information and
may wish to delay the assertion of
BRDY
/
TA
. Thus, the 71215
and 71216 have input pins - BRDYH and TAH respectively -
so that the cache controller may force
BRDY
/
TA
high, regard-
less of the result of the tag comparison inside the 71215/16.
In the case of a cache miss or write through, the system
memory controller (usually combined with the cache control-
ler) becomes completely responsible for generating
BRDY
or
TA
for that bus cycle. For flexibility, the 71215/16 incorporates
two options for merging its own
BRDY
/
TA
output with that
generated by the system memory controller.
One approach is to bus the two signals together. This is the
preferred approach when the cache (including the 71215/16)
is optional, as on a module, since addition or removal of the
cache does not affect the way in which the cache controller
generates
BRDY
/
TA
. Figure 9 shows this approach for the
71215 used with the Pentium. It applies equally to the 71216
and PowerPC. This requires that both
BRDY
/
TA
sources be
tri-statable. The
BRDYOE
and
TAOE
input pins of the 71215
and 71216 are driven by the cache/memory controller, and are
used to enable or disable the 71215/16
BRDY
/
TA
output as
necessary. To be prepared for a possible hit, each new bus
cycle begins with
BRDYOE
/
TAOE
low. In the event of a cache
miss, the controller deasserts
BRDYOE
/
TAOE
, then takes
over responsibility for driving
BRDY
/
TA
. This is also the
procedure for writes to write-through lines, where even cache
hits are responded to by the controller. Also, the controller
usually takes over control of
BRDY
/
TA
for the second, third
and fourth words of a burst transfer. This is required if either
the CPU address is not guaranteed to remain valid throughout
the entire bus cycle (a change to the 71215/16 address bus
Figure 8. 71215/16 BRDY/TA Timing - Chip Set Removed
from the Critical Path
Figure 7. Conventional Tag RAM Usage - Chip Set in BRDY/
TA Critical Path
66MHz CPU
71215/16 TAG
A(0:13)
TAG(0:11)
A(5:30)
STATUS BITS
BRDY
/
TA
MATCH
CACHE
CONTROLLER
10ns
10ns
10ns
Delay
w/
derating
11ns
5ns Setup
Two Clock Cycles = 30ns
3176 drw 08
66MHz CPU
TAG SRAM
CACHE
CONTROLLER
MATCH
10ns
Delay
w/ derating
5ns
Delay
10ns
Delay
5ns Setup
ADDRESS
BRDY
/
TA
Misc. Addr and Status
Two Clock Cycles = 30ns
3176 drw 07
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