参数资料
型号: APA300-FGG144
厂商: Microsemi SoC
文件页数: 154/178页
文件大小: 0K
描述: IC FPGA PROASIC+ 300K 144-FBGA
标准包装: 160
系列: ProASICPLUS
RAM 位总计: 73728
输入/输出数: 100
门数: 300000
电源电压: 2.3 V ~ 2.7 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 144-LBGA
供应商设备封装: 144-FPBGA(13x13)
ProASICPLUS Flash Family FPGAs
v5.9
2-67
Asynchronous FIFO Read
Note: The plot shows the normal operation status.
Figure 2-40 Asynchronous FIFO Read
Table 2-63 TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
ERDH, FRDH,
THRDH
Old EMPTY, FULL, EQTH, & GETH valid hold
time from RB
0.5
ns
Empty/full/thresh are invalid from the end
of hold until the new access is complete
ERDA
New EMPTY access from RB
3.01
ns
FRDA
FULL
↓ access from RB ↑
3.01
ns
ORDA
New DO access from RB
7.5
ns
ORDH
Old DO valid from RB
3.0
ns
RDCYC
Read cycle time
7.5
ns
RDWRS
WB
↑, clearing EMPTY, setup to
RB
3.02
ns
Enabling the read operation
1.0
ns
Inhibiting the read operation
RDH
RB high phase
3.0
ns
Inactive
RDL
RB low phase
3.0
ns
Active
RPRDA
New RPE access from RB
9.5
ns
RPRDH
Old RPE valid from RB
4.0
ns
THRDA
EQTH or GETH access from RB
4.5
ns
Notes:
1. At fast cycles, ERDA and FRDA = MAX (7.5 ns – RDL), 3.0 ns.
2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns – WRL), 3.0 ns.
RB = (RDB+RBLKB)
RPE
RDATA
EMPTY
EQTH, GETH
FULL
(Empty inhibits read)
Cycle Start
WB
tRDWRS
tERDH, tFRDH
tERDA, tFRDA
tTHRDH
tORDH
tRPRDH
tORDA
tRPRDA
tRDL
tRDH
tRPRDA
tRDL
tRDCYC
tRDH
tTHRDA
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