参数资料
| 型号： | AS3658F-BCTP |
| 厂商： | ams |
| 文件页数： | 118/158页 |
| 文件大小： | 0K |
| 描述： | IC PMU POWER/AUDIO 124-CTBGA |
| 标准包装： | 2,500 |
| 应用： | 便携式设备 |
| 电流 - 电源： | 7mA |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 124-TFBGA |
| 供应商设备封装： | 124-CTBGA（8x8） |
| 包装： | 带卷 (TR) |
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AS3658
Data Sheet Confidential
- Detailed Description - System Functions
The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state
(the bus is free). The device-write address is followed by the word address. After the word address any number of data
bytes can be send to the slave. The word address is incriminated internally, in order to write subsequent data bytes on
subsequent address locations.
For reading data from the slave device, the master has to change the transfer direction. This can be done either with a
repeated START condition followed by the device-read address, or simply with a new transmission START followed by
st
the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1 register
byte transmitted from the slave. In Read-Mode any number of subsequent register bytes can be read from the slave.
The word address is incriminated internally.
The diagrams below show various read formats available:
2
Figure 53. I C Random-Read:
S
DW
A
WA
A Sr
DR
A
data
N P
read register
WA++
WA++
Random-Read and Sequential-Read are combined formats. The repeated START condition is used to change the
direction after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START
condition is followed by the device-write address and the word address.
st
In order to change the data direction a repeated START condition is issued on the 1 SCL pulse after the acknowledge
bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In
this state the slave transmits register data located by the previous received word address vector. The master responds
to the data byte with a not-acknowledge, and issues a STOP condition on the bus.
2
Figure 54. I C Sequential-Read:
S
DW
A
WA
A Sr
DR
A
data 1
A
data 2
…
A
data n
N P
read register
WA++
WA++
Sequential-Read is the extended form of Random-Read, as more than one register-data bytes are transferred
subsequently. In difference to the Random-Read, for a sequential read the transferred register-data bytes are
responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited
(consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-
acknowledge following the last data byte and generate the STOP condition subsequently.
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