参数资料
| 型号： | AS3658F-BCTP |
| 厂商： | ams |
| 文件页数： | 125/158页 |
| 文件大小： | 0K |
| 描述： | IC PMU POWER/AUDIO 124-CTBGA |
| 标准包装： | 2,500 |
| 应用： | 便携式设备 |
| 电流 - 电源： | 7mA |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 124-TFBGA |
| 供应商设备封装： | 124-CTBGA（8x8） |
| 包装： | 带卷 (TR) |
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AS3658
Data Sheet Confidential
- Detailed Description - System Functions
10.3
Interrupt Controller
The interrupt controller generates an interrupt request for the host controller as soon as one or more of the bits in the
Interrupt 1…3 register is set by pulling low pin XINT. All the interrupt sources can be enabled in the Interrupt Mask 1…3
register. The Interrupt 1…3 registers are cleared automatically after the host controller has read them. To prevent the
AS3658 device from losing an interrupt event, the register that is read is captured before it is transmitted to the host
controller via the serial interface. As soon as the transmission of the captured value is complete a logical AND
operation with the bit wise inverted captured value is applied to the register to clear all interrupt bits that have already
been transmitted. Clearing the read interrupt bits takes 2 clock cycles, a read access to the same register before the
clearing process has completed will yield a value of ‘0’. Note that an interrupt that has been present at the previous
read access will be cleared as well in case it occurs again before the clearing process has completed.
During a read access to one of the interrupt registers the XINT pin will be released. As soon as the transferred bits of
the interrupt register have been cleared the XINT pin will be pulled low in case a new interrupt has occurred in the
meantime. By doing so the interrupt controller will work correctly with host controllers that are edge- and level-sensitive
on their interrupt request input. Multiple byte read access is recommended to avoid reading the Interrupt 1 register
over and over again in response to a new interrupt that has occurred in the same register (and thus pulling low pin
XINT) before the Interrupt 2,3 register has been read.
Table 131. Interrupt Status 1 Register
Interrupt Status1
Addr:50
These bits show the status of the interrupts
register is reset at power-on-reset and after each read access
Bit
0
1
2
3
4
5
Bit Name
chstate_i
cheoc_i
charging_tmax_i
usb_chdet_i
chdet_i
Onkey_i
Default
NA
NA
NA
NA
NA
NA
Access
R
R
R
R
R
R
Description
Bit is set when the following status bits are set or reset:
Trickle, CVM, NoBat
Bit is set when the EOC status bits are set or reset:
Bit is set when charge timeout ( tricke, CV, CC) has
been expired
Bit is set when the USB_ChDet Bit is set or reset.
Bit is set when the ChDet Bit is set or reset.
Bit is set when status XON bit is set or reset.
Bit is set when the lower temperature threshold
6
ovtmp_i
NA
R
Temp 110 of the temperature sensor is exceeded for
longer than t RESMASK .
7
Lowsup
NA
R
Bit is set when the main supply voltage VSUPPLY has
dropped below V RESFALL for longer than t RESMASK .
Table 132. Interrupt Status 2 Register
Interrupt Status2
Addr:51
These bits show the status of the interrupts
register is reset at power-on-reset and after each read access
Bit
0
Bit Name
sd1_lv_i
Default
NA
Access
R
Description
Bit is set when voltage of step down1 drops below low
voltage threshold (1msec debounce timer)
Bit is set when voltage of step down2 drops below low
1
sd2_lv_i
NA
R
voltage threshold
(1msec debounce timer)
Bit is set when voltage of step down3 drops below low
2
sd3_lv_i
NA
R
voltage threshold
(1msec debounce timer)
www.austriamicrosystems.com
Revision 1v13
124 - 157
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