参数资料
型号: AS3658F-BCTP
厂商: ams
文件页数: 136/158页
文件大小: 0K
描述: IC PMU POWER/AUDIO 124-CTBGA
标准包装: 2,500
应用: 便携式设备
电流 - 电源: 7mA
电源电压: 3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 124-TFBGA
供应商设备封装: 124-CTBGA(8x8)
包装: 带卷 (TR)
AS3658
Data Sheet Confidential
- Detailed Description - System Functions
10.6
Watchdog
The purpose of the watchdog is to detect a deadlock of the software. If the watchdog is active, it must receive a
continuous trigger signal within a programmable time window. If there is no signal anymore for a certain time period
from a defined pad or special serial interface bit, it starts either a complete reset cycle or changes the state of an output
pin, which can be used e.g. as an interrupt to the processor.
The watchdog is highly configurable by the following register bits:
The complete block can be switched on by wtdg_on = 1 and off by wtdg_on = 0.
The watchdog time window is defined by the register wtdg_min_timer and wtdg_max_timer.
The trigger signal can be configured by register wtdg_trigger and wtdg_gpio_input. (Pin CURR1-CURR4 (GPIO1-
GPIO4) or register bit)
If the watchdog expires, the system can start automatically a reset cycle if wtdg_reset_on = 1
Any of the general purpose input / outputs can be configured to output the watchdog signal. The Watchdog delivers
a signal “wtdg_alarm”, which is normal ‘0’ and goes to ‘1’ in the case of a timer-overflow. This signal can be used as
e.g. a reset or interrupt for a processor.
Table 156. Watchdog Register definitions
Addr:60
Watchdog control
These bits control the watchdog functions
Bit
Bit Name
Default
Access
Description
Switches on the complete watchdog
0
wtdg_on
0
R/W
0
watchdog off
1
watchdog enabled
1
wtdg_res_on
1
R/W
If the watchdog expires and wtdg_res_on = 1 a reset
cycle will be started
0
Use the register bit wtdg_sw_signal as trigger
signal for the watchdog
Use one of the GPIO pins CURR1_GPIO1 …
2
wtdg_trigger
0
R/W
1
CURR4_GPIO4 as trigger input for the
watchdog; the actual pin is selected by setting
GPIOXIOSF to 01b(watchdog mode) and
GPIOXMode=010b (GPIO digital input)
(X=1...4)
Table 157. Watchdog minimum timer definitions
Addr:61
Watchdog_min timer
These bits set the watchdog minimum timer
Bit
7:0
Bit Name
Wtdg_min_timer
Default
00h
Access
R/W
Description
Defines the minimum watchdog trigger time
(LSB=7.5ms, range: 0 – 1.9s)
Table 158. Watchdog max timer definitions
Addr:62
Watchdog_max timer
These bits set the watchdog maximum timer
Bit
7:0
Bit Name
Wtdg_max_timer
Default
FFh
Access
R/W
Description
Defines the maximum watchdog trigger time
(LSB=7.5ms, range: 7.5ms – 1.9s), do not set to (00)h
www.austriamicrosystems.com
Revision 1v13
135 - 157
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