参数资料
型号: AS3658F-BCTP
厂商: ams
文件页数: 96/158页
文件大小: 0K
描述: IC PMU POWER/AUDIO 124-CTBGA
标准包装: 2,500
应用: 便携式设备
电流 - 电源: 7mA
电源电压: 3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 124-TFBGA
供应商设备封装: 124-CTBGA(8x8)
包装: 带卷 (TR)
AS3658
Data Sheet Confidential
Table 97. ADC_R Register
Addr:80
- Detailed Description- Audio Functions
ADC_R
These bits control the Audio ADC volume and functions
Bit
Bit Name
Default Access
Description
volume settings for right ADC input, adjustable in 32 steps
@ 1.5dB
00000
-34.5 dB gain
4:0
adr_vol
00000b
R/W
00001
-33 dB gain
.....
11110
11111
0
10.5 dB gain
12 dB gain
normal mode
5
adc2dac
0b
R/W
1
use ADC output as DAC input (for testing
purposes, equalizer is bypassed)
00
Microphone
7:6
adcmux
00b
R/W
01
10
Line In
reserved –do not use
11
Audio Sum (Output of Mixer)
9.5
I2S master mode and PCM Mode
The digital audio interface can also operate in master mode by using I2S1 interface.
The pin MCLK2 is used as clock input in that case. Any input clock between sampling rate and 24MHz may be used as
input clock.
In Master Mode operation SCLK1 as output has 32 clock cycles for each sample word.
SCLK = [MCLK / 4] = [LRCLK * 256 / 4] = LRCK * 64
(EQ 8)
Sample Rates
In Master Mode the i2smaster control allows programming various sample rates. The master clock is generated from
the MCLK2 input. Sampling frequencies from 8kHz to 48kHz can be selected. For certain division ratios between
master clock and sample ratio a certain deviation is system inherent.
LRCLK = f MCLK 2 *
1
2
*
1
RD + 2
Table 98. PLL,i2s_clk_divider settings
Sample rate
kHz
48,000
44,100
32,000
29,400
24,000
22,050
12,000
MCLK2 input
kHz
12288
12288
12288
12288
12288
12288
12288
Divider
126,00
137,32
190,00
206,98
254,00
276,64
510,00
i2s_clk_divider
<10:0>
126
137
190
207
254
277
510
Actual sample
rate
kHz
48,00
44,20
32,00
29,40
24,00
22,02
12,00
Error
%
0,00
0,23
0,00
-0,01
0,00
-0,13
0,00
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Revision 1v13
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