参数资料
| 型号： | BR93L56RF-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 15/41页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 2KBIT 2MHZ 8SOP |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (128 x 16) |
| 速度： | 2MHz |
| 接口： | Microwire 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-SOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1380 (CN2011-ZH PDF) |
| 其它名称： | BR93L56RF-WE2DKR |
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BR93L -W Series, 93A □□ -WM Series, BR93H □□ -WC Series
Technical Note
○ ERASE, ERAL
9 Rise of clock ＊ 2
SK
DI
A1
8
9
A0
Enlarged figure
Start bit
Ope code
Address
*1
1/2
tE/W
(In the case of BR93L46-W/A46-WM )
1bit
2bit
6bit
a ： From start bit to 9 clock rise ＊ 2
Cancel by CS=“L”
b ： 9 clock rise and after ＊ 2
a
b
＊ 1 Address is 8 bits in BR93L56-W/A56-WM, BR93L66-W/A66-WM
Address is 10 bits in BR93L76-W/A76-WM
＊ 2 11 clocks in BR93L56-W/A56-WM, BR93L66-W/A66-WM
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
And when SK clock is input continuously, cancellation is not available.
13 clocks in BR93L76-W/A76-WM
13 Rise of clock
*2
SK
12
13
14
15
DI
D1
a
b
Enlarged figure
c
Start bit
1bit
Ope code
2bit
a
Address
10bit
*1
b
tE/W
c
(In the case of BR93L86-W/A86-WM )
a ： From start bit to 13 clock rise
Cancel by CS=“L”
b ： 13 clock rise and after
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
Note 1) If Vcc is made OFF in this area, designated address data is
not guaranteed, therefore write once again.
c ： 14 clock rise and after
Cancel by CS=“L”
However, when write is started in b area (CS is ended), cancellation is not
available by any means.
And when SK clock is output continuously is not available.
Note 2) If CS is started at the same timing as that of the SK rise,
write execution/cancel becomes unstable, therefore, it is
recommended to fail in SK=”L” area.
As for SK rise, recommend timing of tCSS/tCSH or higher.
Fig.68 ERASE, ERAL cancel available timing
2) At standby
○ Standby current
When CS is “L”, SK input is “L”, DI input is “H”, and even with middle electric potential, current does not increase.
○ Timing
As shown in Fig.69, when SK at standby is “H”, if CS is started, DI status may be read at the rise edge.
At standby and at power ON/OFF, when to start CS, set SK input or DI input to “L” status. (Refer to Fig.70)
CS=SK=DI=”H”
Wrong recognition as a start bit
If CS is started when SK=”L” or DI=”L”, a start
bit is recognized correctly.
CS
Start bit input
CS
Start bit input
SK
DI
Fig.69 Wrong action timing
SK
DI
Fig.70 Normal action timing
www.rohm.com
? 2011 ROHM Co., Ltd. All rights reserved.
15/40
2011.09 - Rev.G
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BR93L56-W | 功能描述:IC EEPROM 2KBIT 2MHZ 8DIP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:2,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 异步 存储容量:256K (32K x 8) 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:28-TSSOP（0.465"，11.8mm 宽） 供应商设备封装:28-TSOP 包装:带卷 (TR) 其它名称:71V256SA15PZGI8 |
| BR93L66 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
| BR93L66F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
| BR93L66FJ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
| BR93L66FJ-W | 制造商:ROHM 制造商全称:Rohm 功能描述:Microwire BUS 4Kbit(256 x 16bit) EEPROM |
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