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参数资料
| 型号： | BU-66318G0-110 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 |
| 封装： | 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208 |
| 文件页数： | 10/32页 |
| 文件大小： | 278K |
| 代理商： | BU-66318G0-110 |
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18
Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
LOCAL PROCESSOR INTERFACE
DMA INTERFACE
The control signals include the standard DMA handshake signals
REQ, GNT, ACK, as well as the transfer control outputs
MEM/REG and RD/WR, the ACE handshake signals SELECT
[5:0] and RDY [5:0], and LOCAL_CS which is used as a chip
select for RAM access.
The BU-66318 ACE-Bridge supports a DMA type local bus inter-
face when a local processor is utilized. When a local CPU is
detected on power-up, via the GNT signal, the local bus interface
is enabled. If the local bus interface is used, the OE/MEM/REG,
WE/RD/WR, ADDRESS, and DATA buses will be tri-stated
unless the bus is granted to the Bolt-On-PCI device or if the
ACE-Bridge is being written to from the local bus (CS asserted).
The ACE-Bridge will take control of the local bus after it asserts
REQ and receives a GNT back. The bus will remain in control of
the ACE-Bridge until it negates ACK. If the local bus interface is
not used all control signals are two-state, not tri-state.
Data transfers between the subsystem (subsystem is defined as
the entire local bus) and the BU-66318 are initiated by means of
a DMA handshake, initiated by the BU-66318. A data read oper-
ation is defined to be the transfer of data from the subsystem to
the BU-66318. Conversely, a data write operation transfers data
from the BU-66318 to the subsystem. Data is transferred as a
single 16-bit word.
DMA READ FROM RAM OPERATION
In response to a PCI read, if the requested address falls within
the local RAM window, the BU-66318 needs to read data words
from the local RAM. To initiate a data word read transfer, the
ACE-Bridge asserts the signal REQ low. Assuming that the local
processor asserts GNT in time, the BU-66318 will then present
a valid address and assert the control signals OE and
LOCAL_CS low, along with ACK low, to enable data to be read
from the local RAM.
Each 32-bit word PCI read operation causes two consecutive 16-bit
words reads to occur from the local RAM. The address is present-
ed for the first word, and then after the Data Word has been written,
the value of the address bus outputs A15 - A0 are incremented.
DMA WRITE TO RAM OPERATION
In response to a PCI write, if the requested address falls within the
local RAM window, the BU-66318 needs to write data words to the
local RAM. To initiate a data word write transfer, the ACE-Bridge
presents valid address and asserts the signal REQ low. Assuming
that the local processor asserts GNT in time, the BU-66318 will
then assert the control signals WE low and LOCAL_CS, along with
ACK low, to enable data to be written to the local RAM.
All write operations are transferred through the BU-66318 to the
subsystem in a contiguous burst. Each 32-bit word PCI write
operation causes two single 16-bit words writes to the local
RAM. The address is presented for the first word, and then after
the Data Word has been written, the value of the address bus
outputs A15 - A0 are incremented.
DMA READ FROM ACE OPERATION
In response to a PCI read, if the requested address is directed
towards ACE RAM or ACE register space, the BU-66318 needs
to read data words from the appropriate ACE RAM or register. To
initiate a data word read transfer, the ACE-Bridge asserts the sig-
nal REQ low. Assuming that the local processor asserts GNT in
time, the BU-66318 will then present valid address and assert the
control signals RD high and MEM/REG high for memory access
or MEM/REG low for register access, along with ACK low.
Following the latter, SELECT is asserted low. The SELECT [5:0]
signal is tied to the corresponding ACEs SELECT and STRBD
inputs. Data is read from the ACE once the RDY [5:0] signal is
asserted low (ACE READYD signal is asserted by the ACE).
Each 32-bit word PCI read operation causes two consecutive 16-
bit word reads to occur from the ACE memory. When reading
ACE registers only a single 16-bit read occurs. In other words, if
the requested read is of an ACE register, only the first half of the
32-bit word transferred back to the PCI bus is valid
DMA WRITE TO ACE OPERATION
In response to a PCI write, if the requested address is directed
towards ACE RAM or ACE register space, the BU-66318 needs to
write the data words to the appropriate ACE RAM or register. To ini-
tiate a data word write transfer, the ACE-Bridge asserts the signal
REQ low. Assuming that the local processor asserts GNT in time,
the BU-66318 will then present valid address and data, assert the
control signals WR low and MEM/REG high for memory access or
MEM/REG low for register access, along with ACK low. Following
the latter, SELECT is asserted low. The SELECT [5:0] signal is tied
to the corresponding ACEs SELECT [5:0] and STRBD inputs. Data
is sampled by the ACE following the RDY [5:0] signal is asserted
low (ACE READYD signal is asserted by the ACE).
Each 32-bit word PCI write operation causes two consecutive
16-bit word writes to occur to ACE memory. When writing to ACE
registers only the first 16-bits of the 32-bit PCI word are written.
ACE ACCESS
The ACE-Bridge accesses the ACE hybrid via the SELECT and
STROBE handshake method. Although the BU-66318 can
access the entire ACE family, the Enhanced Mini-ACE series is
the MIL-STD-1553 terminal of choice. The Enhanced Mini-ACE
is the fastest and contains the most functionality. The Enhanced
Mini-ACE has also remained compatible with software from the
older ACE series parts.
Processor access to the Enhanced Mini-ACE has been greatly
improved. The Enhanced Mini-ACE's maximum host holdoff time
(time prior to the assertion of the READYD handshake signal)
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