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参数资料
| 型号： | BU-66318G0-110 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 |
| 封装： | 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208 |
| 文件页数： | 6/32页 |
| 文件大小： | 278K |
| 代理商： | BU-66318G0-110 |
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14
Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
For easy reference, TABLE 19 provides the timing parameters
for 3.3V PCI signaling environments applicable to the ACE-
Bridge, and FIGURE 6 shows the timing reference points. The
timing parameters apply to the other timing diagrams, but are not
illustrated. The ACE-Bridge conforms to revision 2.2 of the PCI
Local Bus specification.
The timing parameters are provided
here for ease of reference only.
TABLE 19. PCI INTERFACE TIMINGS
SYMBOL
PARAMETER
MIN MAX UNITS
tv
CLK to signal valid delay
ns
11
2
7
0
tsu
th
Input setup time to CLK
Input hold time from CLK
1
2
3
4
5
6
7
th
tsu
tv
th
tsu
th
tsu
th
tsu
th
tsu
PCI single read from PACE configuration space (C/BE# = Ah)
with PCI timing parameters. AD[31:0]: address driven by master; data driven by PACE
ADDRS
DATA
ByteEnables
Ah
0ns
50ns
100ns
150ns
I
PCICLK
IO
AD
I
C/BE[3:0]#
I
FRAME#
I
IRDY#
O
TRDY#
O
STOP#
O
DEVSEL#
I
IDSEL
FIGURE 5 PCI SINGLE READ OF CONFIGURATION SPACE WITH TIMING
FIGURE 5 illustrates a PCI read from the ACE-Bridge's configu-
ration space. The ACE-Bridge only responds to Type Zero con-
figuration access: AD[1:0] must be 00 during the command
phase. The ACE-Bridge will drive a full Dword on the AD lines
independent of which byte enables are asserted during the con-
figuration read.
FIGURE 6 illustrates a PCI single write to ACE-Bridge configu-
ration space. The ACE-Bridge only responds to Type Zero con-
figuration access: AD[1:0] must be 00 during the command
phase. Note that all combinations of byte enables for configura-
tion writes are supported. If no byte enables are asserted during
a burst write to configuration space no internal write will occur,
but the internal address will be incremented.
FIGURE 8 illustrates the process of reading an ACE memory
(BAR0) or ACE register (BAR1 000-5FCh) location, assuming
that there is an ACE present in the specific memory space. The
actual read shown is that of a single word read, due to the
~600 nS response time shown, see following text and timing for-
mula tables. If the write FIFO is empty and there isn't a previous
Delayed Read Request (DRR) pending, a read from these loca-
tions enques a DRR, which is then processed by the ACE-
Bridge. If either of these conditions is true, the ACE-Bridge will
respond with a Retry, but will not enque any new DRR. The
ACE-Bridge uses a DRR mechanism to respond to BA0 and
BAR1 000-5FCh reads because the time required to fetch these
locations from the ACEs present on the local bus is greater than
the PCI data latency rules.
The ACE-Bridge responds to the first read with a Retry. By PCI
rules the master must repeat the same exact request until it com-
pletes.
This is shown by the master's second read attempt,
which also produces a Retry. Each repeated read request from
the master will be target terminated with a Retry until the data
from the enqued DRR is present in the ACE-Bridge's PCI inter-
face.
The successful completion is shown at the third read
request, which produces a Disconnect with Data.
This process applies to any memory read from legal address
space other than the PCI-ACE interface registers at BAR1 offset
800-81Ch.
When reading ACE memory (BAR0), any combination of byte
enables is supported, but the ACE-Bridge will drive the entire
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