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参数资料
| 型号： | BU-66318G0-110 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 |
| 封装： | 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208 |
| 文件页数： | 11/32页 |
| 文件大小： | 278K |
| 代理商： | BU-66318G0-110 |
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19
Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
has been significantly reduced. For ACE/Mini-ACE, this maxi-
mum holdoff time is 10 internal word transfer cycles, resulting in
an overall holdoff time of approximately 2.8 s, using a 16 MHz
clock. When the Enhanced Mini-ACE's ENHANCED CPU
ACCESS feature is used, this worst-case holdoff time is reduced
to a single internal transfer cycle. For example, when operating
the Enhanced Mini-ACE in its 16-bit buffered, non-zero wait con-
figuration with a 16 MHz clock input, this results in a maximum
overall host transfer cycle time of 632 ns for a read cycle, or 570
ns for a write cycle.
FIGURE 10 illustrates a generic connection diagram between
the BU-66318, a 16-bit microprocessor, a local RAM, and an
Enhanced Mini-ACE (decoder configuration is shown to allow for
up to 6 Enhanced Mini-ACEs). The Enhanced Mini-ACE is con-
figured for the 16-bit buffered, Non-Zero Wait configuration. This
configuration may be used to interface between 16-bit or 32-bit
microprocessors and an Enhanced Mini-ACE. In this mode, only
the Enhanced Mini-ACE's 4K or 64K words of internal RAM are
used for storing 1553 message data and associated "house-
keeping" functions. In this configuration the Enhanced Mini-ACE
will never attempt to access memory on the host bus.
FIGURE 11 illustrates the ACE-Bridge reading from an ACE, and
FIGURE 12 illustrates writing to the RAM using "DMA-type" arbi-
tration for the bus.
LOCAL RAM
ENHANCED
Mini-ACE
(DEVICE 0)
BU-66318
PCI - ACE
BRIDGE
LOCAL
CPU
CLOCK
OSCILLATOR
D15-D0
A15-A0
D
1
5
-
D
0
A
1
5
-
A
0
A18-A0
A18-A16
CPU ADDRESS LATCH
(NOTE1)
(NOTE 2)
ADDR-LAT
TRANSPARENT / BUFFERED
+5V
16/8_BIT
TRIGGER_SEL
REQ
GRT
ACK
MSB/LSB
POLARITY_SEL
ZERO_WAIT
SELECT
MEM/REG
ACK
SEL_ACE[0]
OE/MEM/REG
RD/WR
STRBD
READYD
RD/WR
CPU STROBE
CPU ACKNOWLEDGE
RD/WR
WE/RD/WR
WE
CS
OE
SELECT [0]
SELECT [5:0]
READY [5:0]
LOCAL_CS
CS_BU66318
CS
READYD [0]
MSTCLR
INT
N/C
RESET
RST
SID 0
SID 1
BUSMODE 4#
BUSMODE 3#
BUSMODE 2#
BUSMODE 1#
BOLT_ON_EN_L
+5V
INT [0]
LOCAL_IRQ
CPU IRQ
CLK IN
RT
ADDRESS
PARITY
RTAD4-RTAD0
RTADP
+5V
NOTES
1. CPU ADDRESS LATCH SIGNAL PROVIDED BY
PROCESSORS WITH MULTIPLEXED ADDRESS/DATA
BUSES.
2. FOR PROCESSORS WITH SEPARATE ADDRESS/DATA
BUSES, CONNECT ADDR-LAT TO +5V.
3. ASSUMES SUB-SYSTEM VENDOR AND DEVICE ID'S ARE
LOADED INTO THE BU-66318 BY THE CPU ON POWER-UP.
4. BUSMODE SIGNALS MUST BE TIED AS LISTED FOR PCI
APPLICATIONS.
55 Ohm
CH. A
1
2
3
TX/RXA
8
7
5
4
TX/RXA
55 Ohm
CH. B
1
2
3
TX/RXB
8
7
5
4
TX/RXB
ADDRESS
DECODER
INTERRUPT
LOGIC
SEL_ACE[1]
SEL_ACE[2]
SEL_ACE[3]
SEL_ACE[4]
SEL_ACE[5]
OUTPUT_ENA
TS_ENA
AD[31:0]
C/BE[3:0]
PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
REQ#
INT A#
IP_TST_L
PCI_CLK
A[15:0]
D[15:0]
+5V
PCI_TEST_L
+5V
}
INT [5:0]
}
ACE_INT [5:0]
}
RAM_CS
(NOTE 3)
(NC)
(NOTE 4)
55 Ohm
FIGURE 10. BU-66318 ACE-BRIDGE WITH LOCAL CPU, RAM, AND ENHANCED MINI-ACE
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