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参数资料
| 型号： | BU-66318G0-110 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 |
| 封装： | 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208 |
| 文件页数： | 2/32页 |
| 文件大小： | 278K |
| 代理商： | BU-66318G0-110 |
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10
Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
TABLE 9. REG0 GLOBAL ACTIVITY REGISTER
REG0 GLOBAL ACTIVITY REGISTER (READ 800H)
BIT
DESCRIPTION
31 (MSB)
PCI INTERRUPT ACTIVE
30
29
FIFO NOT EMPTY
0
28
LOCAL CPU PRESENT
27
0
26
NUMBER OF ACE'S PRESENT - BIT 2 (MSB)
25
NUMBER OF ACE'S PRESENT - BIT 1
24
23
NUMBER OF ACE'S PRESENT - BIT 0 (LSB)
BAR1 DRR DATA DISCARD
22
FAIL-SAFE ERROR
21
ACE 6 INTERRUPT ACTIVE
20
ACE 5 INTERRUPT ACTIVE
19
ACE 4 INTERRUPT ACTIVE
18
17
ACE 3 INTERRUPT ACTIVE
ACE 2 INTERRUPT ACTIVE
16
ACE 1 INTERRUPT ACTIVE
15
INTERRUPT VECTOR TO PCI - BIT 15 (MSB)
0
INTERRUPT VECTOR TO PCI - BIT 0 (LSB)
TABLE 10. REG1
FAIL-SAFE OPERATION/INTERRUPT REGISTER
(READ/WRITE 804H)
BIT
DESCRIPTION
31 (MSB)
DRR HOLD
30
29
VECTOR IRQ DISABLE
SETUP DELAY FOR LOCAL BUS - BIT 1 (MSB)
28
SETUP DELAY FOR LOCAL BUS - BIT 0 (LSB)
27
LOCAL PROCESSOR INTERRUPT ENABLE
26
ACE6 INTERRUPT ENABLE
25
ACE5 INTERRUPT ENABLE
24
23
ACE4 INTERRUPT ENABLE
ACE3 INTERRUPT ENABLE
22
ACE2 INTERRUPT ENABLE
21
ACE1 INTERRUPT ENABLE
20
BAR1 DRR DATADISCARD INTERRUPT ENABLE
19
FAILSAFE INTERRUPT ENABLE
18
17
FAILSAFE INTERRUPT AUTOCLEAR ENABLE
FAILSAFE MODE - BIT 1 (MSB)
16
FAILSAFE MODE - BIT 0 (LSB)
15
INTERRUPT VECTOR FROM PCI - BIT 15 (MSB)
0
INTERRUPT VECTOR FROM PCI - BIT 0 (LSB)
PCI INTERRUPT ACTIVE: Active HIGH
FIFO NOT EMPTY: When set to '1', indicates that the write FIFO
is not empty. The Write FIFO being not empty impacts the laten-
cy of PCI BAR0 and BAR1 ACE register read operations. See
"PCI read of ACE memory/registers" section for more information.
LOCAL CPU PRESENT: This bit reflects whether the BU-66318
detected a local CPU during initialization. The BU-66318 polls its
GNT input signal for a ground condition following power-up. If the
GNT signal is found to be LOW during power-up, this bit will be
defined as "no local CPU present" and will be set to a value of zero.
When a CPU is found the Local Bus Mode is enabled and the
BU-66318 will arbitrate for the local bus whenever access is
required. In Local Bus Mode, when the BU-66318 is not in con-
trol of the local bus, all of its control signals will be tri-stated.
NUMBER OF ACE'S PRESENT: Bits 26 (MSB) to 24 (LSB) provide
a binary representation of the number of ACE terminals presently
installed and operating. The BU-66318 supports up to six ACE ter-
minals and may be configured for 1, 2, 3, 4, 5 or 6 ACE devices.
BAR1 DRR DATA DISCARD: If the data discard timer times out
while waiting for a retry on a BAR1 access, this bit will be set. If
BAR1 read is discarded, it may have caused an action (for
example clearing an ACE interrupt) that has not been recognized
by the PCI MASTER.
FAIL-SAFE ERROR: If not in FAIL-SAFE OFF mode and fail-safe
error occurs (local CPU or ACE does not respond), this bit will be
set.
ACE INTERRUPT ACTIVE: Bits 21 to 16 reflect the status of the
INT5 to INT0 signal inputs (respectively). The signals INT5 to
INT0 also represent the state of the ACE6 to ACE1 interrupt out-
put signals (respectively). All ACE interrupts must be pro-
grammed for level operation. When an ACE interrupt signal
occurs, the corresponding ACE INTERRUPT ACTIVE bit gets set
to a ONE. Bits 21 to 16 are cleared when the ACE clears its inter-
rupt request line.
Any unused ACE channel should have the corresponding
INT[5:0] input grounded.
INTERRUPT VECTOR TO PCI: Writing to this location by the
local processor causes a PCI interrupt if at least one of the bits
(15-0) is a '1'. Reading this location from the PCI bus clears the
register. This register can be read by local processor to see if
PCI master has read it yet and will not cause it to clear.
Subsequent writes occurring to this register by the local proces-
sor prior to a PCI Master read can set new bits in the register.
Any bits previously set cannot be cleared by new writes. A PCI
Master read can only clear bits in this register.
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