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参数资料
| 型号： | BU-66318G0-110 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 |
| 封装： | 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208 |
| 文件页数： | 17/32页 |
| 文件大小： | 278K |
| 代理商： | BU-66318G0-110 |
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Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
TABLE 26. LOCAL BUS INTERFACE CONTROL
SIGNAL NAME
PIN
DESCRIPTION
SELECT0 (O)
66
SELECT1 (O)
67
SELECT2 (O)
68
SELECT3 (O)
83
SELECT4 (O)
149
SELECT5 (O)
177
RDY0 (I)
69
RDY1 (I)
70
RDY2 (I)
122
RDY3 (I)
97
RDY4 (I)
112
RDY5 (I)
119
INT0 (I)
44
INT1 (I)
61
INT2 (I)
120
INT3 (I)
93
Connected to the respective device [5:0] ACE terminal's SELECT and STRBD signal pins. Address decoder
output to select the ACE for a transfer to/from either RAM or register.
Handshake input from the respective ACE device [5:0] READYD signal pins. For a read access, RDY is
asserted at the end of a host transfer cycle to indicate that data is available to be read on D15 through D0
when asserted (low). For a write cycle, RDY is asserted at the end of the cycle to indicate that data has
been transferred to a register or RAM location. For both reads and writes, the BU-66318 asserts SELECT /
STRBD low until READYD is asserted low.
Interrupt request input from respective ACE devices [5:0]INT signal pins. ACE interrupts are active low sig-
nals.Following a PCI RST#, all connected ACE devices should drive their INT signals inactive high. At this
time the BU-66318 tests its INT [5:0] signals for a low condition. If an active low signal is present, the corre-
sponding ACE device is recorded as "not present".Any unused ACE channel should have its corresponding
INT [5:0] signal grounded.
Read / Write. For ACE or local RAM access, RD/WR selects between reading (RD/WR = 1) and writing
(RD/WR = 0). When the local processor is accessing the ACE-Bridge's internal registers (CS=0) this signal
determines whether an internal register is being written or read.
Memory / Register. For ACE access, MEM/REG selects between ACE memory (MEM/REG = "1") or regis-
ter access (MEM/REG = "0"). When performing a local RAM read, this pin is an output.
Data Transfer Request. Active low level output signal used to request access of the local bus from the local CPU.
Data Transfer Grant. Active low input signal asserted by the local CPU in response to the REQ output to
indicate that control of the local bus has been transferred from the local microprocessor to the ACE-Bridge.
Once asserted, GNT may not be de-asserted prior to the assertion of ACK. GNT must be connected to
ground when a local CPU is not used.
INT4 (I)
96
INT5 (I)
113
RD / WR (I/O)
78
MEM / REG (O)
75
REQ(O)
179
GNT (I)
164
Data Transfer Acknowledge. Active low output signal used to indicate acceptance of the local bus in
response to a data transfer grant GNT. The local bus is always controlled by the BU-66318 during the time
that ACK is asserted low.The BU-66318 will drive all ACE control signals to their in-active (logic '1') state
prior to beginning a transaction and again after completing a transaction, prior to de-asserting ACK.
ACK(O)
178
Chip Select signal input from local CPU indicating that it is accessing BU-66318 internal registers.This sig-
nal must be pulled-up when a local CPU is not used.
CS(I)
175
Chip select signal asserted by BU-66318 when a transfer to local RAM is being performed. When local
RAM is accessed ACE signals RD/WR and MEM/REG will be utilized to generate OE and WE.
LOCAL_CS(O)
9
Interrupt signal to the local processor asserted by the ACE-Bridge in response to any bit being set in REG1
from a PCI write. This signal will remain asserted until the local processor performs a read from the ACE-
Bridge IRQ register.
LOCAL_IRQ(O)
11
Reset signal to the local bus asserted active low following a PCI RST#.
RST(O)
10
Local bus handshake signal to indicate data is valid during a read of the ACE-Bridge's local bus registers
OR that the ACE-Bridge has accepted the data during a write to the ACE-Bridge's internal registers
B_RDY(O)
77
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