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参数资料
| 型号： | BX80524P300000 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 300 MHz, MICROPROCESSOR, PPGA370 |
| 封装： | 1.950 X 1.950 INCH, HEAT SINK, STAGGERED, PLASTIC, PGA-370 |
| 文件页数： | 16/88页 |
| 文件大小： | 1622K |
| 代理商： | BX80524P300000 |
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Intel Celeron Processor
Datasheet
23
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel
Celeron processor frequencies
and cache sizes.
2. VIH and VOH for the Intel Celeron processor may experience excursions of up to 200 mV above VTT for a
single system bus clock. However, input signal drivers must comply with the signal quality specifications in
4. Parameter correlated to measurement into a 25
resistor terminated to 1.5 V.
5. IOH for the Intel Celeron processor may experience excursions of up to 12 mA for a single system bus clock.
6. (0
≤ VIN ≤ 2.0 V +5%).
7. (0
≤ VOUT ≤ 2.0 V +5%).
8. Refer to the I/O Buffer Models for IV characteristics.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel
Celeron processor frequencies.
2. Parameter measured at 14 mA (for use with TTL inputs).
3. (0
≤ VIN ≤ 2.5 V +5%).
4. (0
≤ VOUT ≤ 2.5 V +5%).
2.11
AGTL+ System Bus Specifications
It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination
resistors to VTT at each end of the signal trace. These termination resistors are placed electrically
between the ends of the signal traces and the VTT voltage supply and generally are chosen to
approximate the substrate impedance. The valid high and low levels are determined by the input
buffers using a reference voltage called VREF. Single ended termination may be possible if trace
lengths are tightly controlled, see the Intel 440EX AGPset Design Guide (Order Number 290637)
or the Intel Celeron Processor (PPGA) with the Intel 440LX AGPset Design Guide (Order
Number 245088) for more information.
AGTL+ reference voltage (VREF) is generated on the processor substrate (S.E.P. Package only) for
the processor core, but should be set to 2/3 VTT for other AGTL+ logic using a voltage divider on
the motherboard. It is important that the motherboard impedance be specified and held to a ±20%
tolerance, and that the intrinsic trace capacitance for the AGTL+ signal group traces is known and
well-controlled. For more details on AGTL+, see the Pentium II Processor Developer's Manual
(Order Number 243502) and AP-585, Pentium
II Processor AGTL+ Guidelines (Order Number
243330).
Table 6.
Non-AGTL+ Signal Group DC Specifications 1
Symbol
Parameter
Min
Max
Unit
Notes
VIL
Input Low Voltage
–0.3
0.7
V
VIH
Input High Voltage
1.7
2.625
V
2.5 V +5% maximum
VOL
Output Low Voltage
0.4
V
2
VOH
Output High Voltage
N/A
2.625
V
All outputs are open-
drain to 2.5 V +5%
IOL
Output Low Current
14
mA
IL
Leakage Current for Inputs,
Outputs, and I/O
±100
A
3, 4
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