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参数资料
| 型号： | BX80524P300000 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 300 MHz, MICROPROCESSOR, PPGA370 |
| 封装： | 1.950 X 1.950 INCH, HEAT SINK, STAGGERED, PLASTIC, PGA-370 |
| 文件页数： | 8/88页 |
| 文件大小： | 1622K |
| 代理商： | BX80524P300000 |
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Intel Celeron Processor
16
Datasheet
The PPGA package has more power (88) and ground (80) pins than the S.E.P. Package. Of the
power pins, 77 are used for the processor core (VCC
CORE) and 8 are used as a AGTL+ reference
voltage (VREF). The other 3 power pins are VCC
1.5, VCC2.5 and VCCCMOS and are used for future
processor compatibility.
The VCC
CMOS pin is provided as a feature for future processor support in a flexible design. In such a
design, the VCC
CMOS pin is used to provide the CMOS voltage for use by the platform. Additionally,
2.5 V must be provided to the VCC
2.5 input and 1.5 V must be provided to the VCC1.5 input. The
processor routes the CMOS voltage level through the package that it is compatible with. For
example, future processors requiring 1.5 V CMOS voltage levels route 1.5 V to the VCC
CMOS output.
Each power signal, regardless of package, must meet the specifications stated in Table 4. In
addition, all VCC
CORE pins must be connected to a voltage island while all VSS pins have to connect to
a system ground plane.
2.4
Intel Celeron Processor Decoupling
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. This causes voltages on
power planes to sag below their nominal values if bulk decoupling is not adequate. Care must be
taken in the board design to ensure that the voltage provided to the processor remains within the
specifications listed in Table 4. Failure to do so can result in timing violations or a reduced lifetime
of the component.
2.4.1
Intel Celeron Processor System Bus AGTL+ Decoupling
The S.E.P. Package contains high frequency decoupling capacitance on the processor substrate,
where the PPGA package does not. Therefore, Intel Celeron processors in the PPGA package
require high frequency decoupling on the system motherboard. Bulk decoupling must be provided
on the motherboard for proper AGTL+ bus operation for both packages. See AP-585, Pentium
II
Processor AGTL+ Guidelines (Order Number 243330), AP-587, Pentium II Processor Power
Distribution Guidelines (Order Number 243332), and the Pentium II Processor Developer's
Manual (Order Number 243502) for more information.
2.5
Voltage Identification
The processor’s voltage identification (VID) pins can be used to automatically select the VCC
CORE
voltage from a compatible voltage regulator. There are five VID pins (VID[4:0]) on the S.E.P.
Package, while there are only four (VID[3:0]) on the PPGA package. This is because there are no
Intel Celeron processors in the PPGA package that require more than 2.05 V (see Table 1).
VID pins are not signals, but rather are an open or short circuit to VSS on the processor. The
combination of opens and shorts defines the processor core’s required voltage. The VID pins also
allow for compatibility with current and future Intel Celeron processors.
Note that the ‘11111’ (all opens) ID can be used to detect the absence of a processor core in a given
slot (S.E.P. Package only), as long as the power supply used does not affect the VID signals.
Detection logic and pull-ups should not affect VID inputs at the power source (see Section 7.0).
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