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参数资料
| 型号： | BX80524P300000 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 300 MHz, MICROPROCESSOR, PPGA370 |
| 封装： | 1.950 X 1.950 INCH, HEAT SINK, STAGGERED, PLASTIC, PGA-370 |
| 文件页数： | 7/88页 |
| 文件大小： | 1622K |
| 代理商： | BX80524P300000 |
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Intel Celeron Processor
Datasheet
15
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep
state, by stopping the BCLK input. (See Section 2.2.6.) Once in the Sleep state, the SLP# pin can
be deasserted if another asynchronous system bus event occurs. The SLP# pin has a minimum
assertion of one BCLK period.
2.2.6
Deep Sleep State—State 6
The Deep Sleep state is the lowest power state the processor can enter while maintaining context.
The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from
the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BLCK is
stopped. It is recommended that the BLCK input be held low during the Deep Sleep State.
Stopping of the BCLK input lowers the overall current consumption to leakage levels.
To re-enter the Sleep state, the BLCK input must be restarted. A period of 1 ms (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep State. Once in
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus
while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable behavior.
2.2.7
Clock Control
When the processor is in the Sleep or Deep Sleep states, it will not respond to interrupts or snoop
transactions. PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant
states. PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from
the Deep Sleep state to the Sleep state, PICCLK must be restarted with BCLK.
2.3
Intel Celeron Processor Power and Ground Pins
There are five pins defined on the S.E.P. Package for voltage identification (VID) and there are four
pins on the PPGA package. These pins specify the voltage required by the processor core. These
have been added to cleanly support voltage specification variations on current and future Intel
Celeron processors.
For clean on-chip power distribution, Intel Celeron processors in the S.E.P. Package have 27 VCC
(power) and 30 VSS (ground) inputs. The 27 VCC pins are further divided to provide the different
voltage levels to the components. VCC
CORE inputs for the processor core account for 19 of the VCC
pins, while 4 VTT inputs (1.5 V) are used to provide a AGTL+ termination voltage to the processor.
For only the S.E.P. Package, one VCC
5 pin is provided for Voltage Transient Tools. VCC5 and VCCCORE
must remain electrically separated from each other.
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