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| 型号： | BX80532RC2300B |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 2300 MHz, MICROPROCESSOR |
| 文件页数： | 13/99页 |
| 文件大小： | 4142K |
| 代理商： | BX80532RC2300B |
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20
Datasheet
Electrical Specifications
2.7
Asynchronous GTL+ Signals
The Celeron processor on 0.13 micron process does not utilize CMOS voltage levels for any
signals that connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#,
INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# utilize GTL+ input buffers.
Legacy output FERR# and other non-AGTL+ signals (THERMTRIP# and PROCHOT#) utilize
GTL+ output buffers. All of these signals follow the same DC requirements as AGTL+ signals.
However, the outputs are not actively driven high (during a logical 0 to 1 transition) by the
processor (the major difference between GTL+ and AGTL+). These signals do not have setup or
hold time specifications in relation to BCLK[1:0]. However, all of the Asynchronous GTL+ signals
must be asserted for at least two BCLKs for the processor to recognize them. See Section 2.11 and
Section 2.13 for the DC and AC specifications for the Asynchronous GTL+ signal groups. See
Section 7.2 for additional timing requirements for entering and leaving the low power states.
2.8
Test Access Port (TAP) Connection
Because of the voltage levels supported by other components in the Test Access Port (TAP) logic,
it is recommended that the Celeron processor on 0.13 micron process be first in the TAP chain and
be followed by any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of accepting an input
of the appropriate voltage level. Similar considerations must be made for TCK, TMS, and TRST#.
Two copies of each signal may be required, with each driving a different voltage level.
2.9
System Bus Frequency Select Signals (BSEL[1:0])
The BSEL[1:0] are output signals that are used to select the frequency of the processor input clock
(BCLK[1:0]). Table 5 defines the possible combinations of the signals, and the frequency
associated with each combination. The required frequency is determined by the processor, chipset,
and clock synthesizer. All agents must operate at the same frequency.
The Celeron processor on 0.13 micron process currently operates at a 400 MHz system bus
frequency (selected by a 100 MHz BCLK[1:0] frequency). Individual processors will operate only
at their specified system bus frequency.
For more information about these pins, refer to Section 5.2 and the appropriate Platform Design
Guidelines.
Table 5.
BSEL[1:0] Frequency Table for BCLK[1:0]
BSEL1
BSEL0
Function
L
100 MHz
L
H
RESERVED
H
L
RESERVED
H
RESERVED
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相关代理商/技术参数 |
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|---|---|
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