- 您现在的位置：买卖IC网 > PDF目录256110 > BX80532RC2300B (INTEL CORP) 32-BIT, 2300 MHz, MICROPROCESSOR PDF资料下载
参数资料
| 型号： | BX80532RC2300B |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 2300 MHz, MICROPROCESSOR |
| 文件页数： | 71/99页 |
| 文件大小： | 4142K |
| 代理商： | BX80532RC2300B |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页当前第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页
Datasheet
73
Intel Celeron Processor on 0.13 Micron Process in the 478-Pin Package
BINIT#
Input/
Output
BINIT# (Bus Initialization) may be observed and driven by all processor system
bus agents and if used, must connect the appropriate pins of all such agents. If
the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to
signal any bus condition that prevents reliable future operation.
If BINIT# observation is enabled during power-on configuration and BINIT# is
sampled asserted, symmetric agents reset their bus LOCK# activity and bus
request arbitration state machines. The bus agents do not reset their IOQ and
transaction tracking state machines upon observation of BINIT# activation. Once
the BINIT# assertion has been observed, the bus agents will re-arbitrate for the
system bus and attempt completion of their bus queue and IOQ entries.
If BINIT# observation is disabled during power-on configuration, a central agent
may handle an assertion of BINIT# as appropriate to the error handling
architecture of the system.
BNR#
Input/
Output
BNR# (Block Next Request) is used to assert a bus stall by any bus agent that is
unable to accept new bus transactions. During a bus stall, the current bus owner
cannot issue any new transactions.
BPM[5:0]#
Input/
Output
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals.
They are outputs from the processor that indicate the status of breakpoints and
programmable counters used for monitoring processor performance. BPM[5:0]#
should connect the appropriate pins of all Celeron processor on 0.13 micron
process system bus agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is
a processor output used by debug tools to determine processor debug
readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ#
is used by debug tools to request debug operation of the processor.
Refer to Table 1 for the appropriate Platform Design Guide, and to the ITP700
Debug Port Design Guide
for more detailed information.
NOTE:
These signals do not have on-die termination. Refer to the appropriate
Platform Design Guide for termination requirements.
BPRI#
Input
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor
system bus. It must connect the appropriate pins of all processor system bus
agents. Observing BPRI# active (as asserted by the priority agent) causes all
other agents to stop issuing new requests unless such requests are part of an
ongoing locked operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by deasserting BPRI#.
BR0#
Input/
Output
BR0# drives the BREQ0# signal in the system and is used by the processor to
request the bus. During power-on configuration this pin is sampled to determine
the agent ID = 0.
NOTE:
This signal does not have on-die termination and must be terminated.
BSEL[1:0]
Input/
Output
BSEL[1:0] (Bus Select) are used to select the processor input clock frequency.
Table 5 defines the possible combinations of the signals and the frequency
associated with each combination. The required frequency is determined by the
processor, chipset and clock synthesizer. All agents must operate at the same
frequency. The Celeron processor on 0.13 micron process operates at a
400 MHz system bus frequency (100 MHz BCLK[1:0] frequency). For more
information about these pins including termination recommendations, refer to
Section 2.9 and the appropriate platform design guidelines.
COMP[1:0]
Analog
COMP[1:0] must be terminated on the system board using precision resistors.
Refer to Table 1 for the appropriate Platform Design Guide for details on
implementation.
Table 36. Signal Description (Sheet 2 of 8)
Name
Type
Description
相关PDF资料 |
PDF描述 |
|---|---|
| BU-65743F8-310 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| BU-61559D1-390Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
| BU-61559D1-620Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
| BU-61559D2-330Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
| BU-61559D2-330 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| BX80532RC2500B | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 0.13UM 2.5GHZ 478-PIN FCPGA2 - Boxed Product (Development Kits) |
| BX80532RC2600B | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 0.13UM 2.6GHZ - Boxed Product (Development Kits) |
| BX80532RC2800B | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 0.13UM 2.8GHZ - Boxed Product (Development Kits) |
| BX80536NC1700EJ | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 390 RISC 64-BIT 90NM 1.7GHZ 1.05V - Boxed Product (Development Kits) |
| BX80537T5500 S L9SH | 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5500 64-Bit 65nm 1.66GHz 1.05V 478-Pin FCPGA6 |
发布紧急采购，3分钟左右您将得到回复。