- 您现在的位置：买卖IC网 > PDF目录256110 > BX80532RC2300B (INTEL CORP) 32-BIT, 2300 MHz, MICROPROCESSOR PDF资料下载
参数资料
| 型号： | BX80532RC2300B |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 2300 MHz, MICROPROCESSOR |
| 文件页数： | 76/99页 |
| 文件大小： | 4142K |
| 代理商： | BX80532RC2300B |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页当前第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页
78
Datasheet
Pin Listing and Signal Definitions
SLP#
Input
SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter
the Sleep state. During Sleep state, the processor stops providing internal clock
signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor
will only recognize the assertion of the RESET# signal, deassertion of SLP#, and
removal of the BCLK input while in Sleep state. If SLP# is deasserted, the
processor exits Sleep state and returns to Stop-Grant state, restarting its internal
clock signals to the bus and processor core units.
SMI#
Input
SMI# (System Management Interrupt) is asserted asynchronously by system
logic. On accepting a System Management Interrupt, the processor saves the
current state and enters System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program execution
from the SMM handler.
If SMI# is asserted during the deassertion of RESET#, the processor will tristate
its outputs.
STPCLK#
Input
Assertion of STPCLK# (Stop Clock) causes the processor to enter a low power
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction
and stops providing internal clock signals to all processor core units except the
system bus and APIC units. The processor continues to snoop bus transactions
and service interrupts while in Stop-Grant state. When STPCLK# is deasserted,
the processor restarts its internal clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
TCK
Input
TCK (Test Clock) provides the clock input for the processor Test Bus (also known
as the Test Access Port).
TDI
Input
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO
Output
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides
the serial output needed for JTAG specification support.
TESTHI[12:8]
TESTHI[5:0]
Input
TESTHI[12:8] and TESTHI[5:0] must be connected to a VCC power source
through a resistor for proper processor operation. See Section 2.5 for more
details.
THERMDA
Other
Thermal Diode Anode. See Section 7.3.1.
THERMDC
Other
Thermal Diode Cathode. See Section 7.3.1.
THERMTRIP#
Output
Assertion of THERMTRIP# (Thermal Trip) indicates that the processor junction
temperature has reached a level where permanent silicon damage may occur.
Measurement of the temperature is accomplished through an internal thermal
sensor that is configured to trip at approximately 135 °C. Upon assertion of
THERMTRIP#, the processor will shut off its internal clocks (thus halting program
execution) in an attempt to reduce the processor junction temperature. To protect
the processor, its core voltage (VCC) must be removed following the assertion of
sequence and timing requirements.
For processors with CPUID of 0xF27 and beyond:
Driving of the THERMTRIP# signal is enabled within 10
s of the assertion
of PWRGOOD, and is disabled on de-assertion of PWRGOOD. Once
activated, THERMTRIP# remains latched until PWRGOOD is de-asserted.
While the de-assertion of the PWRGOOD signal will de-assert
THERMTRIP#, if the processor’s junction temperature remains at or above
the trip level, THERMTRIP# will again be asserted within 10
s of the
assertion of PWRGOOD.
TMS
Input
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TRDY#
Input
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to
receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all system bus agents.
Table 36. Signal Description (Sheet 7 of 8)
Name
Type
Description
相关PDF资料 |
PDF描述 |
|---|---|
| BU-65743F8-310 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| BU-61559D1-390Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
| BU-61559D1-620Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
| BU-61559D2-330Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
| BU-61559D2-330 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| BX80532RC2500B | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 0.13UM 2.5GHZ 478-PIN FCPGA2 - Boxed Product (Development Kits) |
| BX80532RC2600B | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 0.13UM 2.6GHZ - Boxed Product (Development Kits) |
| BX80532RC2800B | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 0.13UM 2.8GHZ - Boxed Product (Development Kits) |
| BX80536NC1700EJ | 制造商:Intel 功能描述:MPU CELERON PROCESSOR 390 RISC 64-BIT 90NM 1.7GHZ 1.05V - Boxed Product (Development Kits) |
| BX80537T5500 S L9SH | 制造商:Intel 功能描述:MPU Core?2 Duo Processor T5500 64-Bit 65nm 1.66GHz 1.05V 478-Pin FCPGA6 |
发布紧急采购，3分钟左右您将得到回复。