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| 型号： | BX80532RC2300B |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 2300 MHz, MICROPROCESSOR |
| 文件页数： | 5/99页 |
| 文件大小： | 4142K |
| 代理商： | BX80532RC2300B |
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Datasheet
13
Electrical Specifications
2.0
Electrical Specifications
2.1
System Bus and GTLREF
Most Celeron processor on 0.13 micron process system bus signals use Assisted Gunning
Transceiver Logic (AGTL+) signalling technology. As with the P6 family of microprocessors, this
signalling technology provides improved noise margins and reduced ringing through low voltage
swings and controlled edge rates. Like the Intel Pentium 4 processor, the termination voltage
level for the Celeron processor on 0.13 micron process AGTL+ signals is VCC, which is the
operating voltage of the processor core. The use of a termination voltage that is determined by the
processor core allows better voltage scaling on the system bus for Celeron processor on
0.13 micron process. Because of the speed improvements to data and address bus, signal integrity
and platform design methods have become more critical than with previous processor families.
Design guidelines for the Celeron processor on 0.13 micron process system bus are described in the
appropriate Platform Design Guide (refer to Table 1).
The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine
whether a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board.
Termination resistors are provided on the processor silicon, and are terminated to the processor
core voltage (VCC). Intel chipsets also provide on-die termination, thus eliminating the need to
terminate most AGTL+ signals on the system board.
Some AGTL+ signals do not include on-die termination and must be terminated on the system
board. See Table 4 for details regarding these signals.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
system bus, including trace lengths, is highly recommended when designing a system.
2.2
Power and Ground Pins
For clean on-chip power distribution, the Celeron processor on 0.13 micron process has 85 VCC
(power) and 181 VSS (ground) inputs. All power pins must be connected to VCC, and all VSS pins
must be connected to a system ground plane.The processor VCC pins must be supplied with the
voltage defined by the VID (Voltage ID) pins and the loadline specifications (see Figure 4).
2.3
Decoupling Guidelines
Because of the large number of transistors and high internal clock speeds, the processor is capable
of generating large average current swings between low and full power states. This may cause
voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
Care must be taken in the board design to ensure that the voltage provided to the processor remains
within the specifications listed in Table 7. Failure to do so can result in timing violations and/or
affect the long term reliability of the processor. For further information and design guidelines, refer
VR-Down Design Guidelines.
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