参数资料
型号: C8051F300-TB
厂商: Silicon Laboratories Inc
文件页数: 165/178页
文件大小: 0K
描述: BOARD PROTOTYPING W/C8051F300
标准包装: 1
类型: MCU
适用于相关产品: C8051F300
所含物品:
Rev. 2.9
87
C8051F300/1/2/3/4/5
SFR Definition 9.1.
(Note: Do not use read-modify-write operations (ORL, ANL) on this register)
Bit7:
UNUSED. Read = 0. Write = don’t care.
Bit6:
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
Bit5:
C0RSEF: Comparator0 Reset Enable and Flag.
Write
0: Comparator0 is not a reset source.
1: Comparator0 is a reset source (active-low).
Read
0: Source of last reset was not Comparator0.
1: Source of last reset was Comparator0.
Bit4:
SWRSF: Software Reset Force and Flag.
Write
0: No Effect.
1: Forces a system reset.
Read
0: Source of last reset was not a write to the SWRSF bit.
1: Source of last was a write to the SWRSF bit.
Bit3:
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
Bit2:
MCDRSF: Missing Clock Detector Flag.
Write:
0: Missing Clock Detector disabled.
1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is detected.
Read:
0: Source of last reset was not a Missing Clock Detector timeout.
1: Source of last reset was a Missing Clock Detector timeout.
Bit1:
PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. This may be due to a true power-on reset or
a VDD monitor reset. In either case, data memory should be considered indeterminate fol-
lowing the reset. Writing this bit enables/disables the VDD monitor.
Write:
0: VDD monitor disabled.
1: VDD monitor enabled.
Read:
0: Last reset was not a power-on or VDD monitor reset.
1: Last reset was a power-on or VDD monitor reset; all other reset flags indeterminate.
Bit0:
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
R
R/W
R
R/W
R
Reset Value
FERROR C0RSEF
SWRSF
WDTRSF MCDRSF
PORSF
PINRSF
Variable
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xEF
RSTSRC: Reset Source
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