- 您现在的位置：买卖IC网 > PDF目录366628 > C9832HT Up to 5A ULDO linear regulator PDF资料下载
参数资料
| 型号： | C9832HT |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系统时钟发生器|采用TSSOP | 56PIN |塑料 |
| 文件页数： | 15/24页 |
| 文件大小： | 169K |
| 代理商： | C9832HT |
C9832H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07109 Rev. **
5/24/2001
Page 15 of 24
Approved Product
CPU_STP# - Assertion (transition from logic ‘1’ to logic ‘0’)
When CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via
assertion of CPU_STP# will be stopped after being sampled by 2 falling CPU clock edges. The final state of the
stopped CPU signals is CPU = high and CPU0# = Low. There is no change to the output drive current values during
the stopped state. The CPU is driven high with a current value equal to (Mult 0 ‘select’) x (Iref), and the CPU# signal
will not be driven. Due to external pulldown circuitry CPU# will be low during this stopped state.
CPU_STP#
CPU
CPU#
Assertion CPU_STP# Waveform Figure
CPU_STP# Functionality Table
CPU_STP#
1
0
CPU#4
Normal
Iref*Mult
CPU
Normal
Float
DRCG
66M
66M
66CLK(0:2)
66Input
66Input
PCI_F/PCI
66Input/2
66Input/2
PCI
USB/DOT
48M
48M
66Input/2
66Input/2
CPU_STP# De-assertion (transition from logic ‘0’ to logic ‘1’)
The de-assertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation
in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produces
when the clock resumes. The maximum latency from the de-assertion to active outputs is no more than 2 CPU clock
cycles.
相关PDF资料 |
PDF描述 |
|---|---|
| C9832HY | N-CHANNEL 60V - 0.014 Ohm - 60A TO-220/TO220FP STRIPFET POWER MOSFET |
| C9860-21 | 3 BAND EQUALIZER AUDIO PROCESSOR WITH SUBWOOFER CONTROL |
| C9860-22 | QUAD 2 CHANNEL MULTIPLEXER |
| C9860-23 | QUAD 2 CHANNEL MULTIPLEXER |
| C9860-24 | EXTERNALLY ADJUSTABLE MULTIFUNCTION REGULATOR |
相关代理商/技术参数 |
参数描述 |
|---|---|
| C9832HY | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU SYSTEM CLOCK GENERATOR|SSOP|56PIN|PLASTIC |
| C98332-000 | 制造商:TE Connectivity 功能描述:QLL405 - Labels that come on sheets or rolls 制造商:TE Connectivity 功能描述:C98332-000 |
| C9835 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems |
| C9835CT | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems |
| C9835CTT | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems |
发布紧急采购，3分钟左右您将得到回复。