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参数资料
| 型号： | C9832HT |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系统时钟发生器|采用TSSOP | 56PIN |塑料 |
| 文件页数： | 17/24页 |
| 文件大小： | 169K |
| 代理商： | C9832HT |
C9832H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07109 Rev. **
5/24/2001
Page 17 of 24
Approved Product
PD# (Power Down) Clarification
The PD# (Power Down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an
asynchronous active low input. This signal is synchronized internally to the device powering down the clock
synthesizer. PD# is an asynchronous function for powering up the system. When PD# is low, all clocks are driven to a
low value and held there and the VCO and PLL’s are also powered down. All clocks are shut down in a synchronous
manner so has not to cause glitches while transitioning to the low ‘stopped’ state.
PD# Functionality
PD#
1
0
CPU
Normal
Iref*2
CPU#
Normal
Float Low
DRCG
66M
Low
66CLK (0:2)
66Input
Low
PCI_F/PCI
66Input/2
Low
PCI
USB/DOT
48M
Low
66Input/2
Low
PD# - Assertion (transition from logic ’l’ to logic ‘0’)- Buffered Mode
When PD# is sampled low by two consecutive rising edges of the CPU# clock, then on the next high to low transition
of PCIF, the PCIF clock is stopped low. On the next high to low transition of 66Buff, the 66Buff clock is stopped low.
From this time, each clock will stop low on it’s next high to low transition. After the last clock has stopped, the rest of
the generator may be shut down.
all clock outputs except CPU clocks are held low on their next high to low transition. CPU clocks are held with the
CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. Note the example below shows CPU = 100M,
this diagram and description is applicable for all other valid CPU frequencies.
Stopping of the REF clock outputs may take more than one clock cycle to complete.
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