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参数资料
| 型号： | C9832HT |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系统时钟发生器|采用TSSOP | 56PIN |塑料 |
| 文件页数： | 9/24页 |
| 文件大小： | 169K |
| 代理商： | C9832HT |
C9832H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07109 Rev. **
5/24/2001
Page 9 of 24
Approved Product
AC Parameters (Cont.)
66 MHz
Min
45
69.8413
1.0
133 MHz
Min
45
69.8413
1.0
100 MHz
Min
45
69.8413
1.0
200 MHz
Min
Symbol
TDC
TPeriod
Tr / Tf
Parameter
REF Duty Cycle
REF period
REF rise and fall
times
REF Cycle to
Cycle Jitter
Max
55
71.0
4.0
Max
55
71.0
4.0
Max
55
71.0
4.0
Max
Units
%
nS
nS
Notes
2, 4
2, 4
2, 3
TCCJ
-
1000
-
1000
-
1000
pS
2, 4
tpZL, tpZH
Output enable
delay (all outputs)
Output disable
delay (all outputs)
All clock
Stabilization from
power-up
Stopclock Set Up
Time
Stopclock Hold
Time
Oscillator startup
time
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
nS
11
tpLZ, tpZH
1.0
10.0
1.0
10.0
1.0
10.0
1.0
10.0
nS
11
tstable
-
3
-
3
-
3
-
3
mS
11
tss
10.0
-
10.0
-
10.0
-
nS
10
tsh
0
-
0
-
0
-
nS
10
tsu
-
X
-
X
-
X
mS
12
(VDD = VDDA = 3.3V
±
5%, TA = 0
°
C to +70
°
C)
Note 1:
Note 2:
Note 3:
This parameter is measured as an average over 1uS duration, with a crystal center frequency of 14.31818MHz
All outputs loaded as per table 5 below.
Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement
setup section of this data sheet)
Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals (see test and measurement setup section of this
data sheet).
This measurement is applicable with Spread ON or Spread OFF.
Measured from Vol = 0.14V to Voh = 0.56V.
Measured from Vol = 0.2V to Voh = 0.8V..
The time specified is measured from when all VDD’s reach their supply rail (3.3V) till the frequency output is stable and operating within
the specifications.
Measured from when both SEL1 and SEL0 are low
Note 10:
CPU_STP# and PCI_STP# setup time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next
PCI_F clock’s rising edge.
Note 11:
When Xin is driven from an external clock source.
Note 12:
When Crystal meets minimum 40 ohm device series resistance specification.
Note 13:
Measured between 0.2Vdd and .7Vdd
Note 14:
This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to
30/70 but the REF clock duty cycle will not be within data sheet specifications.
Note 15:
Vpullup(external)=1.5V, Min=(Vpullup(external)/2)-150mV, Max=(Vpullup(external)/2)+150mV
Note 16:
Vp = V pull-up (external), Vdif specifies the minimum input differential voltage (Vtr-Vcp) required for switching, where Vtr is the true input
level and Vcp is the compliment input level.
Note 17:
Measured at Vx
Note 18:
This figure is additive to any jitter already present when the 66IN pin is being used as an input. Otherwise a 500 ps jitter figure is
specified.
Note 19:
THIGH is measured at 2.4V for non host outputs.
Note 20:
TLOW is measured at 0.4V for all outputs.
Note 21:
Determined at a fraction of 2*(Trise-Tfall)/ (Trise+Tfall).
Note 22:
Test load is Rta=33.2 ohms, Rd=49.9 ohms.
Note 23:
These crossing points refer to only crossing points containing a rising edge of a Host output.
Note 24:
This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Note 25:
The goal is 150-420pS (1V/nS min rise time across 0.42V).
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
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