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参数资料
| 型号： | C9832HT |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系统时钟发生器|采用TSSOP | 56PIN |塑料 |
| 文件页数： | 5/24页 |
| 文件大小： | 169K |
| 代理商： | C9832HT |
C9832H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07109 Rev. **
5/24/2001
Page 5 of 24
Approved Product
Byte 4: DRCG Control Register
(all bits are read and write functional)
Bit
7
@Pup
0
Pin#
-
Description
SS2 Spread Spectrum control bit
(0=down spread, 1=Center spread)
Reserved
3V66_0 Output Enabled
1 = enabled, 0 = disabled
3V66_1/VCH Output Enable
1 = enabled, 0 = disabled
3V66_5 Output Enable
1 = enabled, 0 = disabled
66B2/3V66_4 Output Enabled
1 = enabled, 0 = disabled
66B1/3V66_3 Output Enabled
1 = enabled, 0 = disabled
66B0/3V66_2 Output Enabled
1 = enabled, 0 = disabled
6
5
0
1
-
33
4
1
35
3
1
24
2
1
23
1
1
22
0
1
21
Byte 6: Silicon Signature Register
(all bits are read only)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
1
1
Pin#
-
-
-
-
-
-
-
-
Description
Vendor Code
011 = IMI
Note:
When writing to this register the device will acknowledge the
write operation, but the data itself will be ignored.
Byte 8: Dial-a-Frequency Control Register N
(all bits are read and write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Pin#
0
0
0
0
0
0
0
0
Description
N7, MSB
N6
N5
N4
N3
N2
N3
N0, LSB
Byte 5: Clock control register
(all bits are read and write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
0
0
0
0
0
0
Pin#
-
-
-
-
-
-
-
-
Description
SS1 Spread Spectrum control bit
SS0 Spread Spectrum control bit
66IN to 66M delay Control MSB
66IN to 66M delay Control LSB
48MDOT edge rate control MSB
48MDOT edge rate control LSB
USB edge rate control MSB
USB edge rate control LSB
Byte 7: Watch Dog Time Stamp Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Pin#
-
-
-
-
-
-
-
-
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 9: Dial-a-Frequency Control Register R
(all bits are read and write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Pin#
-
-
-
-
-
-
-
-
Description
R6 MSB
R5
R4
R3
R2
R1
R0, LSB
R and N register load gate 0=gate closed
(data is latched), 1=gate open (data is
loading from SMBus registers into R and
N)
66IN to 66M Delay Control Table
Byte5
Bit5
Bit4
0
0
1
1
Delay (ns)
0
1
0
1
4.29
4.43
3.95 (default)
3.95
Note:
See App. Notes AN0025 and AN0026 for Dial-a-Frequency
and Dial-a-db.
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