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参数资料
| 型号： | C9832HT |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系统时钟发生器|采用TSSOP | 56PIN |塑料 |
| 文件页数： | 8/24页 |
| 文件大小： | 169K |
| 代理商： | C9832HT |
C9832H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07109 Rev. **
5/24/2001
Page 8 of 24
Approved Product
AC Parameters (Cont.)
66 MHz
Min
45
133 MHz
Min
45
100 MHz
Min
45
200 MHz
Min
45
Symbol
TDC
Parameter
66B(0:2) Duty
Cycle
66B(0:2) rise and
fall times
Any 66B to any
66B Skew
66IN to 66B(0:2)
propagation delay
66B(0:2) Cycle to
Cycle Jitter
Max
55
Max
55
Max
55
Max
55
Units
%
Notes
2, 4
Tr / Tf
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
nS
2, 3
TSKEW
-
175
-
175
-
175
175
pS
2, 4
Tpd
2.5
4.5
2.5
4.5
2.5
4.5
2.5
4.5
nS
2, 4
TCCJ
-
100
-
100
-
100
pS
2, 4, 18
TDC
PCI_F(0:2) PCI
(0:6) Duty Cycle
PCI_F(0:2) PCI
(0:6) period
PCI_F(0:2) PCI
(0:6) high time
PCI_F(0:2) PCI
(0:6) low time
PCI_F(0:2) PCI
(0:6) rise and fall
times
Any PCI clock to
Any PCI clock
Skew
PCI_F(0:2) PCI
(0:6) Cycle to
Cycle Jitter
45
55
45
55
45
55
45
55
%
2, 4
TPeriod
30.0
-
30.0
-
30.0
-
30
-
nS
1, 2, 4
THIGH
12.0
-
12.0
-
12.0
-
12.0
-
nS
19
TLOW
12.0
-
12.0
-
12.0
-
12.0
-
nS
20
Tr / Tf
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
nS
3
TSKEW
-
500
-
500
-
500
-
500
pS
2, 4
TCCJ
-
250
-
250
-
250
-
250
pS
2, 4
TDC
USB48M Duty
Cycle
USB48M period
USB48M rise and
fall times
USB48M Cycle to
Cycle Jitter
45
55
45
55
45
55
45
55
%
2, 4
TPeriod
Tr / Tf
20.8299
1.0
20.8333
2.0
20.8299
1.0
20.8333
2.0
20.8299
1.0
20.8333
2.0
20.8299
1.0
20.8333
2.10
nS
nS
2, 4
2, 3
TCCJ
-
350
-
350
-
350
-
350
pS
1, 2, 4
TDC
DOT48 Duty
Cycle
DOT48 period
DOT48 rise and
fall times
DOT48Cycle to
Cycle Jitter
45
55
45
55
45
55
45
55
%
2, 4
TPeriod
Tr / Tf
20.8299
0.5
20.8333
1.0
20.8299
0.5
20.8333
1.0
20.8299
0.5
20.8333
1.0
20.8299
0.5
20.8333
1.0
nS
nS
2, 4
2, 4
TCCJ
-
350
-
350
-
350
-
350
pS
2, 4
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